On Tue, 2019-06-04 at 17:58 +0300, Imre Deak wrote:
> The HW completion flag for the TBT AUX power well enabling/disabling
> gets stuck if the firmware tears down the TBT DP tunnel before the
> completion.
>
> We shouldn't complain about the timeout, since it's expected to
> happen
> and doesn't cause further issues. We suppress the disabling timeout
> already, do the same for enabling.
This was documented in spec?
>
> Cc: José Roberto de Souza <jose.so...@intel.com>
> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
> Signed-off-by: Imre Deak <imre.d...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display_power.c | 15 ++++++++++-----
> 1 file changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display_power.c
> b/drivers/gpu/drm/i915/intel_display_power.c
> index 278a7edc94f5..249a5fa55df6 100644
> --- a/drivers/gpu/drm/i915/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/intel_display_power.c
> @@ -268,11 +268,16 @@ static void
> hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
> int pw_idx = power_well->desc->hsw.idx;
>
> /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us.
> */
> - WARN_ON(intel_wait_for_register(&dev_priv->uncore,
> - regs->driver,
> - HSW_PWR_WELL_CTL_STATE(pw_idx),
> - HSW_PWR_WELL_CTL_STATE(pw_idx),
> - 1));
> + if (intel_wait_for_register(&dev_priv->uncore,
> + regs->driver,
> + HSW_PWR_WELL_CTL_STATE(pw_idx),
> + HSW_PWR_WELL_CTL_STATE(pw_idx),
> + 1)) {
> + DRM_DEBUG_KMS("%s forced off\n", power_well->desc-
> >name);
Maybe "%s power well enable timeout"?
Anyways we can fix that latter.
Reviewed-by: José Roberto de Souza <jose.so...@intel.com>
> +
> + /* An AUX timeout is expected if the TBT DP tunnel is
> down. */
> + WARN_ON(!power_well->desc->hsw.is_tc_tbt);
> + }
> }
>
> static u32 hsw_power_well_requesters(struct drm_i915_private
> *dev_priv,
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