Quoting Mika Kuoppala (2019-05-24 09:03:00) > Chris Wilson <ch...@chris-wilson.co.uk> writes: > > > From: Dongwon Kim <dongwon....@intel.com> > > > > Setting bit5 (headerless msg for preemptable GPGPU context) of SAMPLER_MODE > > register to enable support for the headless msgs on gen11. None of existing > > use cases will be affected by this as this change makes both types of > > message > > - headerless and w/ header supported at the same time. It also complies with > > the new recommendation for the default bit value for the next gen. > > > > v2: rewrote commit message to include more information > > v3: setting the bit in icl_ctx_workarounds_init() > > > > Signed-off-by: Dongwon Kim <dongwon....@intel.com> > > Reviewed-by: Mika Kuoppala <mika.kuopp...@linux.intel.com>
And pushed. Thanks for the patch and review, -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
