>-----Original Message-----
>From: De Marchi, Lucas
>Sent: Thursday, May 23, 2019 1:24 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Jani Nikula <jani.nik...@linux.intel.com>; Srivatsa, Anusha
><anusha.sriva...@intel.com>; Vivi, Rodrigo <rodrigo.v...@intel.com>; De
>Marchi, Lucas <lucas.demar...@intel.com>
>Subject: [PATCH 06/10] drm/i915/dmc: extract function to parse dmc_header
>
>Complete the extraction of functions to parse specific parts of the firmware.
>The
>return of the function parse_csr_fw() is now redundant since it already sets
>the
>dmc_payload field. Changing it is left for later to avoid noise in the commit.
>
>Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.sriva...@intel.com>
>---
> drivers/gpu/drm/i915/intel_csr.c | 102 ++++++++++++++++++-------------
> 1 file changed, 60 insertions(+), 42 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_csr.c
>b/drivers/gpu/drm/i915/intel_csr.c
>index b19742becb98..20dd4bd5feae 100644
>--- a/drivers/gpu/drm/i915/intel_csr.c
>+++ b/drivers/gpu/drm/i915/intel_csr.c
>@@ -332,6 +332,61 @@ static u32 find_dmc_fw_offset(const struct
>intel_fw_info *fw_info,
> return dmc_offset;
> }
>
>+static u32 parse_csr_fw_dmc(struct intel_csr *csr,
>+ const struct intel_dmc_header *dmc_header) {
>+ unsigned int i, payload_size;
>+ u32 r;
>+ u8 *payload;
>+
>+ if (sizeof(struct intel_dmc_header) != dmc_header->header_len) {
>+ DRM_ERROR("DMC firmware has wrong dmc header length "
>+ "(%u bytes)\n",
>+ (dmc_header->header_len));
>+ return 0;
>+ }
>+
>+ /* Cache the dmc header info. */
>+ if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
>+ DRM_ERROR("DMC firmware has wrong mmio count %u\n",
>+ dmc_header->mmio_count);
>+ return 0;
>+ }
>+
>+ csr->mmio_count = dmc_header->mmio_count;
>+ for (i = 0; i < dmc_header->mmio_count; i++) {
>+ if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
>+ dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
>+ DRM_ERROR("DMC firmware has wrong mmio address
>0x%x\n",
>+ dmc_header->mmioaddr[i]);
>+ return 0;
>+ }
>+ csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
>+ csr->mmiodata[i] = dmc_header->mmiodata[i];
>+ }
>+
>+ /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
>+ payload_size = dmc_header->fw_size * 4;
>+ if (payload_size > csr->max_fw_size) {
>+ DRM_ERROR("DMC FW too big (%u bytes)\n", payload_size);
>+ return 0;
>+ }
>+ csr->dmc_fw_size = dmc_header->fw_size;
>+
>+ csr->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
>+ if (!csr->dmc_payload) {
>+ DRM_ERROR("Memory allocation failed for dmc payload\n");
>+ return 0;
>+ }
>+
>+ r = sizeof(struct intel_dmc_header);
>+ payload = (u8 *)(dmc_header) + r;
>+ memcpy(csr->dmc_payload, payload, payload_size);
>+ r += payload_size;
>+
>+ return r;
>+}
>+
> static u32
> parse_csr_fw_package(struct intel_csr *csr,
> const struct intel_package_header *package_header, @@ -
>418,9 +473,8 @@ static u32 *parse_csr_fw(struct drm_i915_private *dev_priv,
> struct intel_dmc_header *dmc_header;
> struct intel_csr *csr = &dev_priv->csr;
> const struct stepping_info *si = intel_get_stepping_info(dev_priv);
>- u32 readcount = 0, nbytes;
>- u32 i, r;
>- u32 *dmc_payload;
>+ u32 readcount = 0;
>+ u32 r;
>
> if (!fw)
> return NULL;
>@@ -443,47 +497,11 @@ static u32 *parse_csr_fw(struct drm_i915_private
>*dev_priv,
>
> /* Extract dmc_header information. */
> dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
>- if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
>- DRM_ERROR("DMC firmware has wrong dmc header length "
>- "(%u bytes)\n",
>- (dmc_header->header_len));
>- return NULL;
>- }
>- readcount += sizeof(struct intel_dmc_header);
>-
>- /* Cache the dmc header info. */
>- if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
>- DRM_ERROR("DMC firmware has wrong mmio count %u\n",
>- dmc_header->mmio_count);
>- return NULL;
>- }
>- csr->mmio_count = dmc_header->mmio_count;
>- for (i = 0; i < dmc_header->mmio_count; i++) {
>- if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
>- dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
>- DRM_ERROR("DMC firmware has wrong mmio address
>0x%x\n",
>- dmc_header->mmioaddr[i]);
>- return NULL;
>- }
>- csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
>- csr->mmiodata[i] = dmc_header->mmiodata[i];
>- }
>-
>- /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
>- nbytes = dmc_header->fw_size * 4;
>- if (nbytes > csr->max_fw_size) {
>- DRM_ERROR("DMC FW too big (%u bytes)\n", nbytes);
>- return NULL;
>- }
>- csr->dmc_fw_size = dmc_header->fw_size;
>-
>- dmc_payload = kmalloc(nbytes, GFP_KERNEL);
>- if (!dmc_payload) {
>- DRM_ERROR("Memory allocation failed for dmc payload\n");
>+ r = parse_csr_fw_dmc(csr, dmc_header);
>+ if (!r)
> return NULL;
>- }
>
>- return memcpy(dmc_payload, &fw->data[readcount], nbytes);
>+ return csr->dmc_payload;
> }
>
> static void intel_csr_runtime_pm_get(struct drm_i915_private *dev_priv)
>--
>2.21.0
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