On Wed, 20 Mar 2013 09:43:00 -0700
Ben Widawsky <b...@bwidawsk.net> wrote:
> BIOS should be setting this, but in case it doesn't...
>
> v2: Define the bits we actually want to clear (Jesse)
> Make it an RMW op (Jesse)
>
> Signed-off-by: Ben Widawsky <b...@bwidawsk.net>
> ---
> drivers/gpu/drm/i915/i915_gem.c | 6 ++++++
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 8a2cbee..f2d4970 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -3991,6 +3991,12 @@ i915_gem_init_hw(struct drm_device *dev)
> if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
> I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
>
> + if (HAS_PCH_NOP(dev)) {
> + u32 temp = I915_READ(GEN7_MSG_CTL);
> + temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
> + I915_WRITE(GEN7_MSG_CTL, temp);
> + }
> +
> i915_gem_l3_remap(dev);
>
> i915_gem_init_swizzling(dev);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 176cf5c..a627756 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3481,6 +3481,9 @@
> #define DISP_ARB_CTL 0x45000
> #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
> #define DISP_FBC_WM_DIS (1<<15)
> +#define GEN7_MSG_CTL 0x45010
> +#define WAIT_FOR_PCH_RESET_ACK (1<<1)
> +#define WAIT_FOR_PCH_FLR_ACK (1<<0)
>
> /* GEN7 chicken */
> #define GEN7_COMMON_SLICE_CHICKEN1 0x7010
Reviewed-by: Jesse Barnes <jbar...@virtuousgeek.org>
--
Jesse Barnes, Intel Open Source Technology Center
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