In this patch, gamma and degamma hw blobs are created for GLK.
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
v5: -Returned blob instead of assigning it internally within the
function [Ville]
-Renamed glk_get_color_config() to glk_read_luts() [Ville]
-Added glk_read_degamma_lut_linear() to validate degamma blob [Ville]
Signed-off-by: Swati Sharma <swati2.sha...@intel.com>
---
drivers/gpu/drm/i915/intel_color.c | 50 ++++++++++++++++++++++++++++++++++++--
1 file changed, 48 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 1807cb97..32cea6d 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -1410,6 +1410,38 @@ static void i965_read_luts(struct intel_crtc_state
*crtc_state)
}
static struct drm_property_blob *
+glk_read_degamma_lut_linear(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 i, val, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
+ enum pipe pipe = crtc->pipe;
+ struct drm_property_blob *blob;
+ struct drm_color_lut *blob_data;
+
+ I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0);
+ I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT);
+
+ blob = drm_property_create_blob(&dev_priv->drm,
+ sizeof(struct drm_color_lut) * lut_size,
+ NULL);
+ if (IS_ERR(blob))
+ return NULL;
+
+ blob_data = blob->data;
+
+ for (i = 0; i < lut_size; i++) {
+ val = I915_READ(PRE_CSC_GAMC_DATA(pipe));
+
+ blob_data[i].red = REG_FIELD_GET(PRE_CSC_GAMC_MASK, val);
+ blob_data[i].green = REG_FIELD_GET(PRE_CSC_GAMC_MASK, val);
+ blob_data[i].blue = REG_FIELD_GET(PRE_CSC_GAMC_MASK, val);
+ }
+
+ return blob;
+}
+
+static struct drm_property_blob *
glk_read_degamma_lut(struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -1488,6 +1520,19 @@ static void icl_read_luts(struct intel_crtc_state
*crtc_state)
crtc_state->base.gamma_lut = bdw_read_lut_10(crtc_state,
PAL_PREC_INDEX_VALUE(0));
}
+static void glk_read_luts(struct intel_crtc_state *crtc_state)
+{
+ if (crtc_state->csc_enable)
+ crtc_state->base.degamma_lut =
glk_read_degamma_lut_linear(crtc_state);
+ else
+ crtc_state->base.degamma_lut = glk_read_degamma_lut(crtc_state);
+
+ if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+ else
+ crtc_state->base.gamma_lut = bdw_read_lut_10(crtc_state,
PAL_PREC_INDEX_VALUE(0));
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1532,9 +1577,10 @@ void intel_color_init(struct intel_crtc *crtc)
if (INTEL_GEN(dev_priv) >= 11) {
dev_priv->display.load_luts = icl_load_luts;
dev_priv->display.read_luts = icl_read_luts;
- }
- else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
dev_priv->display.load_luts = glk_load_luts;
+ dev_priv->display.read_luts = glk_read_luts;
+ }
else if (INTEL_GEN(dev_priv) >= 8)
dev_priv->display.load_luts = bdw_load_luts;
else if (INTEL_GEN(dev_priv) >= 7)
--
1.9.1
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