GSE interrupts are always enabled on PCH split platforms, so remove the
redundant enable for ASLE. Moreover, the same interrupt bit was used on all
PCH split platforms, even though the bit definitions changed in IVB, thus
unmasking a reserved bit.
Signed-off-by: Jani Nikula <jani.nik...@intel.com>
---
An alternative to this patch would be keeping GSE interrupts masked until
separately enabled. The question is, when are we ready to handle GSE
interrupts? And if we need to care about that, would the right choice be to
mask the interrupts, or rather tell the BIOS through opregion ARDY/DRDY
fields that we are not ready yet?
I chose the approach in this patch because it's the smallest change towards
being more correct; removing a NOP unmask for ILK+SNB and removing a bogus
unmask for IVB and later.
Let the bikeshedding begin. ;)
---
drivers/gpu/drm/i915/i915_irq.c | 16 +++++++---------
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2139714..ba47ec0 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -98,17 +98,15 @@ void intel_enable_asle(struct drm_device *dev)
if (IS_VALLEYVIEW(dev))
return;
+ /* GSE interrupt is always enabled */
+ if (HAS_PCH_SPLIT(dev))
+ return;
+
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- if (HAS_PCH_SPLIT(dev))
- ironlake_enable_display_irq(dev_priv, DE_GSE);
- else {
- i915_enable_pipestat(dev_priv, 1,
- PIPE_LEGACY_BLC_EVENT_ENABLE);
- if (INTEL_INFO(dev)->gen >= 4)
- i915_enable_pipestat(dev_priv, 0,
- PIPE_LEGACY_BLC_EVENT_ENABLE);
- }
+ i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
+ if (INTEL_INFO(dev)->gen >= 4)
+ i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}
--
1.7.9.5
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