Em seg, 2019-03-25 às 14:49 -0700, Daniele Ceraolo Spurio escreveu:
> They now work on uncore, so use raw_uncore_ prefix. Also move them to
> uncore.h
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
> Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
> Cc: Chris Wilson <ch...@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 32 ++-----------------
> drivers/gpu/drm/i915/i915_vgpu.c | 6 ++--
> drivers/gpu/drm/i915/intel_uncore.c | 48 ++++++++++++++---------------
> drivers/gpu/drm/i915/intel_uncore.h | 27 ++++++++++++++++
> 4 files changed, 57 insertions(+), 56 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4e30f7b19b51..558d40f07ffe 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3507,32 +3507,6 @@ static inline u64 intel_rc6_residency_us(struct
> drm_i915_private *dev_priv,
> #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
> #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
>
> -#define __raw_read(x, s) \
> -static inline uint##x##_t __raw_i915_read##x(const struct intel_uncore
> *uncore, \
> - i915_reg_t reg) \
> -{ \
> - return read##s(uncore->regs + i915_mmio_reg_offset(reg)); \
> -}
> -
> -#define __raw_write(x, s) \
> -static inline void __raw_i915_write##x(const struct intel_uncore *uncore, \
> - i915_reg_t reg, uint##x##_t val) \
> -{ \
> - write##s(val, uncore->regs + i915_mmio_reg_offset(reg)); \
> -}
> -__raw_read(8, b)
> -__raw_read(16, w)
> -__raw_read(32, l)
> -__raw_read(64, q)
> -
> -__raw_write(8, b)
> -__raw_write(16, w)
> -__raw_write(32, l)
> -__raw_write(64, q)
> -
> -#undef __raw_read
> -#undef __raw_write
> -
> /* These are untraced mmio-accessors that are only valid to be used inside
> * critical sections, such as inside IRQ handlers, where forcewake is
> explicitly
> * controlled.
> @@ -3559,9 +3533,9 @@ __raw_write(64, q)
> * therefore generally be serialised, by either the dev_priv->uncore.lock or
> * a more localised lock guarding all access to that bank of registers.
> */
> -#define I915_READ_FW(reg__) __raw_i915_read32(&dev_priv->uncore, (reg__))
> -#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(&dev_priv->uncore,
> (reg__), (val__))
> -#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(&dev_priv->uncore,
> (reg__), (val__))
> +#define I915_READ_FW(reg__) __raw_uncore_read32(&dev_priv->uncore, (reg__))
> +#define I915_WRITE_FW(reg__, val__) __raw_uncore_write32(&dev_priv->uncore,
> (reg__), (val__))
> +#define I915_WRITE64_FW(reg__, val__)
> __raw_uncore_write64(&dev_priv->uncore, (reg__), (val__))
> #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
>
> /* "Broadcast RGB" property */
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.c
> b/drivers/gpu/drm/i915/i915_vgpu.c
> index 3d0b493e4200..94d3992b599d 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.c
> +++ b/drivers/gpu/drm/i915/i915_vgpu.c
> @@ -66,17 +66,17 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
>
> BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
>
> - magic = __raw_i915_read64(uncore, vgtif_reg(magic));
> + magic = __raw_uncore_read64(uncore, vgtif_reg(magic));
> if (magic != VGT_MAGIC)
> return;
>
> - version_major = __raw_i915_read16(uncore, vgtif_reg(version_major));
> + version_major = __raw_uncore_read16(uncore, vgtif_reg(version_major));
> if (version_major < VGT_VERSION_MAJOR) {
> DRM_INFO("VGT interface version mismatch!\n");
> return;
> }
>
> - dev_priv->vgpu.caps = __raw_i915_read32(uncore, vgtif_reg(vgt_caps));
> + dev_priv->vgpu.caps = __raw_uncore_read32(uncore, vgtif_reg(vgt_caps));
>
> dev_priv->vgpu.active = true;
> DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index 1816eeae3ba9..3f74889c4212 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -31,7 +31,7 @@
> #define FORCEWAKE_ACK_TIMEOUT_MS 50
> #define GT_FIFO_TIMEOUT_MS 10
>
> -#define __raw_posting_read(uncore__, reg__)
> (void)__raw_i915_read32((uncore__), (reg__))
> +#define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
Now the person trying to figure out what __raw_posting_read() does will
have to chase __raw_uncore_read32(), which is not even greppable. I'm
not sure this is an improvement to our codebase, but the neatness of
just passing everything does have some value. Not really a big deal, so
I'm not blocking merging on this.
>
> static const char * const forcewake_domain_names[] = {
> "render",
> @@ -279,7 +279,7 @@ static inline u32 gt_thread_status(struct intel_uncore
> *uncore)
> {
> u32 val;
>
> - val = __raw_i915_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
> + val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
> val &= GEN6_GT_THREAD_STATUS_CORE_MASK;
>
> return val;
> @@ -306,7 +306,7 @@ static void fw_domains_get_with_thread_status(struct
> intel_uncore *uncore,
>
> static inline u32 fifo_free_entries(struct intel_uncore *uncore)
> {
> - u32 count = __raw_i915_read32(uncore, GTFIFOCTL);
> + u32 count = __raw_uncore_read32(uncore, GTFIFOCTL);
>
> return count & GT_FIFO_FREE_ENTRIES_MASK;
> }
> @@ -451,7 +451,7 @@ static void intel_uncore_edram_detect(struct
> drm_i915_private *dev_priv)
> if (IS_HASWELL(dev_priv) ||
> IS_BROADWELL(dev_priv) ||
> INTEL_GEN(dev_priv) >= 9) {
> - dev_priv->edram_cap = __raw_i915_read32(&dev_priv->uncore,
> + dev_priv->edram_cap = __raw_uncore_read32(&dev_priv->uncore,
> HSW_EDRAM_CAP);
Indentation is now broken for this line above.
With those 2 super important details addressed or not:
Reviewed-by: Paulo Zanoni <paulo.r.zan...@intel.com>
>
> /* NB: We can't write IDICR yet because we do not have gt funcs
> @@ -470,11 +470,11 @@ fpga_check_for_unclaimed_mmio(struct intel_uncore
> *uncore)
> {
> u32 dbg;
>
> - dbg = __raw_i915_read32(uncore, FPGA_DBG);
> + dbg = __raw_uncore_read32(uncore, FPGA_DBG);
> if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
> return false;
>
> - __raw_i915_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
> + __raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
>
> return true;
> }
> @@ -484,11 +484,11 @@ vlv_check_for_unclaimed_mmio(struct intel_uncore
> *uncore)
> {
> u32 cer;
>
> - cer = __raw_i915_read32(uncore, CLAIM_ER);
> + cer = __raw_uncore_read32(uncore, CLAIM_ER);
> if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
> return false;
>
> - __raw_i915_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
> + __raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
>
> return true;
> }
> @@ -498,11 +498,11 @@ gen6_check_for_fifo_debug(struct intel_uncore *uncore)
> {
> u32 fifodbg;
>
> - fifodbg = __raw_i915_read32(uncore, GTFIFODBG);
> + fifodbg = __raw_uncore_read32(uncore, GTFIFODBG);
>
> if (unlikely(fifodbg)) {
> DRM_DEBUG_DRIVER("GTFIFODBG = 0x08%x\n", fifodbg);
> - __raw_i915_write32(uncore, GTFIFODBG, fifodbg);
> + __raw_uncore_write32(uncore, GTFIFODBG, fifodbg);
> }
>
> return fifodbg;
> @@ -537,10 +537,10 @@ static void __intel_uncore_early_sanitize(struct
> intel_uncore *uncore,
>
> /* WaDisableShadowRegForCpd:chv */
> if (IS_CHERRYVIEW(i915)) {
> - __raw_i915_write32(uncore, GTFIFOCTL,
> - __raw_i915_read32(uncore, GTFIFOCTL) |
> - GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
> - GT_FIFO_CTL_RC6_POLICY_STALL);
> + __raw_uncore_write32(uncore, GTFIFOCTL,
> + __raw_uncore_read32(uncore, GTFIFOCTL) |
> + GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
> + GT_FIFO_CTL_RC6_POLICY_STALL);
> }
>
> iosf_mbi_punit_acquire();
> @@ -1068,7 +1068,7 @@ ilk_dummy_write(struct intel_uncore *uncore)
> /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
> * the chip from rc6 before touching it for real. MI_MODE is masked,
> * hence harmless to write 0 into. */
> - __raw_i915_write32(uncore, MI_MODE, 0);
> + __raw_uncore_write32(uncore, MI_MODE, 0);
> }
>
> static void
> @@ -1110,7 +1110,7 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv,
> static u##x \
> gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace)
> { \
> GEN2_READ_HEADER(x); \
> - val = __raw_i915_read##x(uncore, reg); \
> + val = __raw_uncore_read##x(uncore, reg); \
> GEN2_READ_FOOTER; \
> }
>
> @@ -1119,7 +1119,7 @@ static u##x \
> gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace)
> { \
> GEN2_READ_HEADER(x); \
> ilk_dummy_write(uncore); \
> - val = __raw_i915_read##x(uncore, reg); \
> + val = __raw_uncore_read##x(uncore, reg); \
> GEN2_READ_FOOTER; \
> }
>
> @@ -1189,7 +1189,7 @@ func##_read##x(struct drm_i915_private *dev_priv,
> i915_reg_t reg, bool trace) {
> fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \
> if (fw_engine) \
> __force_wake_auto(uncore, fw_engine); \
> - val = __raw_i915_read##x(uncore, reg); \
> + val = __raw_uncore_read##x(uncore, reg); \
> GEN6_READ_FOOTER; \
> }
> #define __gen6_read(x) __gen_read(gen6, x)
> @@ -1226,7 +1226,7 @@ __gen6_read(64)
> static void \
> gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val,
> bool trace) { \
> GEN2_WRITE_HEADER; \
> - __raw_i915_write##x(uncore, reg, val); \
> + __raw_uncore_write##x(uncore, reg, val); \
> GEN2_WRITE_FOOTER; \
> }
>
> @@ -1235,7 +1235,7 @@ static void \
> gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val,
> bool trace) { \
> GEN2_WRITE_HEADER; \
> ilk_dummy_write(uncore); \
> - __raw_i915_write##x(uncore, reg, val); \
> + __raw_uncore_write##x(uncore, reg, val); \
> GEN2_WRITE_FOOTER; \
> }
>
> @@ -1271,7 +1271,7 @@ gen6_write##x(struct drm_i915_private *dev_priv,
> i915_reg_t reg, u##x val, bool
> GEN6_WRITE_HEADER; \
> if (NEEDS_FORCE_WAKE(offset)) \
> __gen6_gt_wait_for_fifo(uncore); \
> - __raw_i915_write##x(uncore, reg, val); \
> + __raw_uncore_write##x(uncore, reg, val); \
> GEN6_WRITE_FOOTER; \
> }
>
> @@ -1283,7 +1283,7 @@ func##_write##x(struct drm_i915_private *dev_priv,
> i915_reg_t reg, u##x val, boo
> fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \
> if (fw_engine) \
> __force_wake_auto(uncore, fw_engine); \
> - __raw_i915_write##x(uncore, reg, val); \
> + __raw_uncore_write##x(uncore, reg, val); \
> GEN6_WRITE_FOOTER; \
> }
> #define __gen8_write(x) __gen_write(gen8, x)
> @@ -1470,7 +1470,7 @@ static void intel_uncore_fw_domains_init(struct
> intel_uncore *uncore)
> * before the ecobus check.
> */
>
> - __raw_i915_write32(uncore, FORCEWAKE, 0);
> + __raw_uncore_write32(uncore, FORCEWAKE, 0);
> __raw_posting_read(uncore, ECOBUS);
>
> fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
> @@ -1478,7 +1478,7 @@ static void intel_uncore_fw_domains_init(struct
> intel_uncore *uncore)
>
> spin_lock_irq(&uncore->lock);
> fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER);
> - ecobus = __raw_i915_read32(uncore, ECOBUS);
> + ecobus = __raw_uncore_read32(uncore, ECOBUS);
> fw_domains_put(uncore, FORCEWAKE_RENDER);
> spin_unlock_irq(&uncore->lock);
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h
> b/drivers/gpu/drm/i915/intel_uncore.h
> index d345e5ab04a5..f7670cbc41c9 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -215,6 +215,33 @@ int intel_wait_for_register_fw(struct drm_i915_private
> *dev_priv,
> 2, timeout_ms, NULL);
> }
>
> +/* register access functions */
> +#define __raw_read(x__, s__) \
> +static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore
> *uncore, \
> + i915_reg_t reg) \
> +{ \
> + return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
> +}
> +
> +#define __raw_write(x__, s__) \
> +static inline void __raw_uncore_write##x__(const struct intel_uncore
> *uncore, \
> + i915_reg_t reg, u##x__ val) \
> +{ \
> + write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
> +}
> +__raw_read(8, b)
> +__raw_read(16, w)
> +__raw_read(32, l)
> +__raw_read(64, q)
> +
> +__raw_write(8, b)
> +__raw_write(16, w)
> +__raw_write(32, l)
> +__raw_write(64, q)
> +
> +#undef __raw_read
> +#undef __raw_write
> +
> #define raw_reg_read(base, reg) \
> readl(base + i915_mmio_reg_offset(reg))
> #define raw_reg_write(base, reg, value) \
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