On Thu, Mar 07, 2019 at 09:59:39AM -0800, Rodrigo Vivi wrote:
> On Thu, Mar 07, 2019 at 12:32:35PM +0200, Imre Deak wrote:
> > Pretend that we have only 1 DBuf slice and that 1 slice is always
> > enabled, until we have a proper way for on-demand toggling of the second
> > slice. Currently we'll try to incorrectly enable DBuf even when all
> > pipes are disabled and we are already runtime suspended (as the computed
> > number of DBuf slices will be 1 in that case).
> >
> > This also means we'll leave the second slice enabled redundantly (except
> > when suspended), but that's an acceptable tradeoff until we have a
> > proper solution.
>
> redundant is the word of the week :)
>
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108756
> > Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.d...@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 7 ++++++-
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 12 ++++++++++--
> > 2 files changed, 16 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 9c97a95c1816..bece16ae6d15 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3624,7 +3624,12 @@ static u8 intel_enabled_dbuf_slices_num(struct
> > drm_i915_private *dev_priv)
> > if (INTEL_GEN(dev_priv) < 11)
> > return enabled_slices;
> >
> > - if (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
> > + /*
> > + * FIXME: for now we'll only ever use 1 slice; pretend that we have
> > + * only that 1 slice enabled until we have a proper way for on-demand
> > + * toggling of the second slice.
> > + */
> > + if (0 && I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
>
> what if just add a check for enabled_slices >= 2 and avoid the FIXME here?
You mean >= 1 during state verification? That would also need its own
FIXME:) And this one here matches better what we do elsewhere to keep
things working.
>
> but up to you:
>
> Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com>
>
> > enabled_slices++;
> >
> > return enabled_slices;
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index aa974b11928a..676a89bb8194 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -3576,7 +3576,11 @@ static void icl_dbuf_enable(struct drm_i915_private
> > *dev_priv)
> > !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
> > DRM_ERROR("DBuf power enable timeout\n");
> > else
> > - dev_priv->wm.skl_hw.ddb.enabled_slices = 2;
> > + /*
> > + * FIXME: for now pretend that we only have 1 slice, see
> > + * intel_enabled_dbuf_slices_num().
> > + */
> > + dev_priv->wm.skl_hw.ddb.enabled_slices = 1;
> > }
> >
> > static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
> > @@ -3591,7 +3595,11 @@ static void icl_dbuf_disable(struct drm_i915_private
> > *dev_priv)
> > (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
> > DRM_ERROR("DBuf power disable timeout!\n");
> > else
> > - dev_priv->wm.skl_hw.ddb.enabled_slices = 0;
> > + /*
> > + * FIXME: for now pretend that the first slice is always
> > + * enabled, see intel_enabled_dbuf_slices_num().
> > + */
> > + dev_priv->wm.skl_hw.ddb.enabled_slices = 1;
> > }
> >
> > static void icl_mbus_init(struct drm_i915_private *dev_priv)
> > --
> > 2.13.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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