On Thu, Nov 29, 2018 at 07:55:03PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> Rename the punit display power register to match the spec.
>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
Reviewed-by: Imre Deak <imre.d...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_cdclk.c | 14 +++++++-------
> drivers/gpu/drm/i915/intel_pm.c | 6 +++---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 12 ++++++------
> 4 files changed, 17 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 47baf2fe8f71..42d25872ecfe 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1020,7 +1020,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> /* See configdb bunit SB addr map */
> #define BUNIT_REG_BISOC 0x11
>
> -#define PUNIT_REG_DSPFREQ 0x36
> +#define PUNIT_REG_DSPSSPM 0x36
> #define DSPFREQSTAT_SHIFT_CHV 24
> #define DSPFREQSTAT_MASK_CHV (0x1f <<
> DSPFREQSTAT_SHIFT_CHV)
> #define DSPFREQGUAR_SHIFT_CHV 8
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> b/drivers/gpu/drm/i915/intel_cdclk.c
> index 25e3aba9cded..82f60f8a15e9 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -468,7 +468,7 @@ static void vlv_get_cdclk(struct drm_i915_private
> *dev_priv,
> cdclk_state->vco);
>
> mutex_lock(&dev_priv->pcu_lock);
> - val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
> + val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
> mutex_unlock(&dev_priv->pcu_lock);
>
> if (IS_VALLEYVIEW(dev_priv))
> @@ -542,11 +542,11 @@ static void vlv_set_cdclk(struct drm_i915_private
> *dev_priv,
> intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
>
> mutex_lock(&dev_priv->pcu_lock);
> - val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
> + val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
> val &= ~DSPFREQGUAR_MASK;
> val |= (cmd << DSPFREQGUAR_SHIFT);
> - vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
> - if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
> + vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
> + if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
> DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
> 50)) {
> DRM_ERROR("timed out waiting for CDclk change\n");
> @@ -622,11 +622,11 @@ static void chv_set_cdclk(struct drm_i915_private
> *dev_priv,
> intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
>
> mutex_lock(&dev_priv->pcu_lock);
> - val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
> + val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
> val &= ~DSPFREQGUAR_MASK_CHV;
> val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
> - vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
> - if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
> + vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
> + if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
> DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
> 50)) {
> DRM_ERROR("timed out waiting for CDclk change\n");
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a26b4eddda25..a67ec01dd958 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -335,12 +335,12 @@ static void chv_set_memory_pm5(struct drm_i915_private
> *dev_priv, bool enable)
>
> mutex_lock(&dev_priv->pcu_lock);
>
> - val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
> + val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
> if (enable)
> val |= DSP_MAXFIFO_PM5_ENABLE;
> else
> val &= ~DSP_MAXFIFO_PM5_ENABLE;
> - vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
> + vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
>
> mutex_unlock(&dev_priv->pcu_lock);
> }
> @@ -6082,7 +6082,7 @@ void vlv_wm_get_hw_state(struct drm_device *dev)
> if (IS_CHERRYVIEW(dev_priv)) {
> mutex_lock(&dev_priv->pcu_lock);
>
> - val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
> + val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
> if (val & DSP_MAXFIFO_PM5_ENABLE)
> wm->level = VLV_WM_LEVEL_PM5;
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 1c2de9b69a19..af499d4a0c66 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -1494,7 +1494,7 @@ static bool chv_pipe_power_well_enabled(struct
> drm_i915_private *dev_priv,
>
> mutex_lock(&dev_priv->pcu_lock);
>
> - state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
> + state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe);
> /*
> * We only ever set the power-on and power-gate states, anything
> * else is unexpected.
> @@ -1506,7 +1506,7 @@ static bool chv_pipe_power_well_enabled(struct
> drm_i915_private *dev_priv,
> * A transient state at this point would mean some unexpected party
> * is poking at the power controls too.
> */
> - ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
> + ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe);
> WARN_ON(ctrl << 16 != state);
>
> mutex_unlock(&dev_priv->pcu_lock);
> @@ -1527,20 +1527,20 @@ static void chv_set_pipe_power_well(struct
> drm_i915_private *dev_priv,
> mutex_lock(&dev_priv->pcu_lock);
>
> #define COND \
> - ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) ==
> state)
> + ((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) ==
> state)
>
> if (COND)
> goto out;
>
> - ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
> + ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
> ctrl &= ~DP_SSC_MASK(pipe);
> ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
> - vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
> + vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, ctrl);
>
> if (wait_for(COND, 100))
> DRM_ERROR("timeout setting power well state %08x (%08x)\n",
> state,
> - vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
> + vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM));
>
> #undef COND
>
> --
> 2.18.1
>
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