Op 05-02-2019 om 17:08 schreef Ville Syrjala:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> On g4x+ we depend on the primary plane DSPCNTR gamma/csc enable
> bits for the pipe bottom color. To guarantee that those are
> correct already when enabling the crtc let's do an explicit
> ->disable_plane() call before enabling the pipe.
>
> On skl+ this will be handled by the explicit PIPE_BOTTOM_COLOR
> register which is already part of the normal color commit we
> do durign crtc enable.
>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_color.c | 4 ++++
> drivers/gpu/drm/i915/intel_display.c | 17 +++++++++++++++++
> 2 files changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index 5c7789e9fed5..79c3adaefadc 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -663,6 +663,10 @@ intel_color_add_affected_planes(struct intel_crtc_state
> *new_crtc_state)
> intel_atomic_get_old_crtc_state(state, crtc);
> struct intel_plane *plane;
>
> + if (!new_crtc_state->base.active ||
> + drm_atomic_crtc_needs_modeset(&new_crtc_state->base))
> + return 0;
Why the needs_modeset skip? We will have already added all planes anyway, but
still.
Oh well, assuming it's for a good reason
Reviewed-by: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
> if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable &&
> new_crtc_state->csc_enable == old_crtc_state->csc_enable)
> return 0;
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index c802055d23a6..f36ac23f7195 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5715,6 +5715,14 @@ static void intel_encoders_update_pipe(struct drm_crtc
> *crtc,
> }
> }
>
> +static void intel_disable_primary_plane(const struct intel_crtc_state
> *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> +
> + plane->disable_plane(plane, crtc_state);
> +}
> +
> static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> struct drm_atomic_state *old_state)
> {
> @@ -5780,6 +5788,8 @@ static void ironlake_crtc_enable(struct
> intel_crtc_state *pipe_config,
> */
> intel_color_load_luts(pipe_config);
> intel_color_commit(pipe_config);
> + /* update DSPCNTR to configure gamma for pipe bottom color */
> + intel_disable_primary_plane(pipe_config);
>
> if (dev_priv->display.initial_watermarks != NULL)
> dev_priv->display.initial_watermarks(old_intel_state,
> pipe_config);
> @@ -5909,6 +5919,9 @@ static void haswell_crtc_enable(struct intel_crtc_state
> *pipe_config,
> */
> intel_color_load_luts(pipe_config);
> intel_color_commit(pipe_config);
> + /* update DSPCNTR to configure gamma/csc for pipe bottom color */
> + if (INTEL_GEN(dev_priv) < 9)
> + intel_disable_primary_plane(pipe_config);
>
> /*
> * Display WA #1153: enable hardware to bypass the alpha math
> @@ -6274,6 +6287,8 @@ static void valleyview_crtc_enable(struct
> intel_crtc_state *pipe_config,
>
> intel_color_load_luts(pipe_config);
> intel_color_commit(pipe_config);
> + /* update DSPCNTR to configure gamma for pipe bottom color */
> + intel_disable_primary_plane(pipe_config);
>
> dev_priv->display.initial_watermarks(old_intel_state,
> pipe_config);
> @@ -6331,6 +6346,8 @@ static void i9xx_crtc_enable(struct intel_crtc_state
> *pipe_config,
>
> intel_color_load_luts(pipe_config);
> intel_color_commit(pipe_config);
> + /* update DSPCNTR to configure gamma for pipe bottom color */
> + intel_disable_primary_plane(pipe_config);
>
> if (dev_priv->display.initial_watermarks != NULL)
> dev_priv->display.initial_watermarks(old_intel_state,
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