Quoting Talha Nassar (2019-02-01 01:08:44)
> Enables blend optimization for floating point RTs
>
> This restores the workaround that was reverted in c358514ba8da
> ("Revert "drm/i915/icl: WaEnableFloatBlendOptimization"").
>
> The revert was due to the register write seemingly not sticking,
> but the HW team has confirmed that this is because the
> register is WO and that the workaround is indeed required.
>
> Here the wa is added with a mask of 0 since the register is WO.
>
> References: https://hsdes.intel.com/resource/1408134172
> References: https://bugs.freedesktop.org/show_bug.cgi?id=107338
> Cc: Chris Wilson <ch...@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com>
>
> Signed-off-by: Talha Nassar <talha.nas...@intel.com>
Vouching for the code, not the hw,
Reviewed-by: Chris Wilson <ch...@chris-wilson.co.uk>
-Chris
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