From: Ville Syrjälä <ville.syrj...@linux.intel.com>
The code managing the dbuf slices is borked and needs some
real work to fix. In the meantime let's just stop using the
second slice.
Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8b63afa3a221..1e41c899ffe2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3618,7 +3618,8 @@ static u8 intel_enabled_dbuf_slices_num(struct
drm_i915_private *dev_priv)
enabled_slices = 1;
/* Gen prior to GEN11 have only one DBuf slice */
- if (INTEL_GEN(dev_priv) < 11)
+ /* FIXME dbuf slice code is broken: see intel_get_ddb_size() */
+ if (1 || INTEL_GEN(dev_priv) < 11)
return enabled_slices;
if (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
@@ -3827,8 +3828,13 @@ static u16 intel_get_ddb_size(struct drm_i915_private
*dev_priv,
/*
* 12GB/s is maximum BW supported by single DBuf slice.
+ *
+ * FIXME dbuf slice code is broken:
+ * - must wait for planes to stop using the slice before powering it off
+ * - plane straddling both slices is illegal in multi-pipe scenarios
+ * - should validate we stay within the hw bandwidth limits
*/
- if (num_active > 1 || total_data_bw >= GBps(12)) {
+ if (0 && (num_active > 1 || total_data_bw >= GBps(12))) {
ddb->enabled_slices = 2;
} else {
ddb->enabled_slices = 1;
--
2.19.2
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