On Thu, Feb 07, 2013 at 03:23:24PM +0100, Daniel Vetter wrote: > Some early bios versions seem to ship with the wrong tuning values for > the MCH, possible resulting in pipe underruns under load. Especially > on DP outputs this can lead to black screen, since DP really doesn't > like an occasional whack from an underrun. > > Unfortunately the registers seem to be locked after boot, so the only > thing we can do is politely point out issues and suggest a BIOS > upgrade. > > Arthur Runyan pointed us at this issue while discussion DP bugs - thus > far no confirmation from a bug report yet that it helps. But at least > some of my machines here have wrong values, so this might be useful in > understanding bug reports. > > Cc: Runyan, Arthur J <arthur.j.run...@intel.com> > Signed-off-by: Daniel Vetter <daniel.vet...@ffwll.ch> > --- > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ > drivers/gpu/drm/i915/intel_pm.c | 34 ++++++++++++++++++++++++++++++++++ > 2 files changed, 42 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 8754f91..b3915cf 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1235,6 +1235,14 @@ > #define MAD_DIMM_A_SIZE_SHIFT 0 > #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) > > +/** snb MCH registers for priority tuning */ > +#define MCH_TC_RFP_C0 (MCHBAR_MIRROR_BASE_SNB + > 0x4294) > +#define MCH_TC_RFP_C1 (MCHBAR_MIRROR_BASE_SNB + > 0x4694) > +#define TC_RFP_OREF_MASK 0xff > +#define TC_RFP_OREF_VAL 0xff > +#define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10) > +#define MCH_SSKPD_WM0_MASK 0x3f > +#define MCH_SSKPD_WM0_VAL 0xc
According to the bug report I'm reading, there are several valid values, so I think you should do some more work. [snip] -- Ben Widawsky, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
