== Series Details == Series: drm/i915/cnl: Fix the formulae for register offsets URL : https://patchwork.freedesktop.org/series/52960/ State : warning
== Summary == $ dim checkpatch origin/drm-tip f3f5633bd407 drm/i915/cnl: Fix the formulae for register offsets -:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #6: For gen10+ the offsets for Slice PG cntl/ EU PG cntl donot scale well for higher slices. -:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'slice' - possible side-effects? #21: FILE: drivers/gpu/drm/i915/i915_reg.h:8665: +#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * \ + ((((slice) / 3) == 1) ? 0x34 : 0x2C) \ + + ((slice) % 3) * 0x4) -:31: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'slice' - possible side-effects? #31: FILE: drivers/gpu/drm/i915/i915_reg.h:8673: +#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * \ + ((((slice) / 3) == 1) ? 0x30 : 0x28) \ + + ((slice) % 3) * 0x8) -:37: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'slice' - possible side-effects? #37: FILE: drivers/gpu/drm/i915/i915_reg.h:8677: +#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * \ + ((((slice) / 3) == 1) ? 0x30 : 0x28) \ + + ((slice) % 3) * 0x8) total: 0 errors, 1 warnings, 3 checks, 27 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
