On Fri, 2018-10-26 at 09:45 -0700, Rodrigo Vivi wrote:
> On Thu, Oct 25, 2018 at 06:17:29PM -0700, José Roberto de Souza
> wrote:
> > It should always wait for idle state when disabling PSR because PSR
> > could be inactive due a call to intel_psr_exit() and while PSR is
> > still being disabled asynchronously userspace could change the
> > modeset causing a call to psr_disable() that will not wait for PSR
> > idle and then PSR will be enabled again while PSR is still not
> > idle.
> >
> > v2: rebased on top of the patch reusing psr_exit()
> >
> > Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
> > Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_psr.c | 41 ++++++++++++++------------
> > ------
> > 1 file changed, 18 insertions(+), 23 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index f698b3f45c6d..4c226b78c3fc 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -661,8 +661,12 @@ static void intel_psr_exit(struct
> > drm_i915_private *dev_priv)
> > {
> > u32 val;
> >
> > - if (!dev_priv->psr.active)
> > + if (!dev_priv->psr.active) {
> > + if (INTEL_GEN(dev_priv) >= 9)
>
> This should be PSR2 check instead of platform no?!
I did not changed this because this code was just moved but yes we
should check if psr2 is enabled.
>
> > + WARN_ON(I915_READ(EDP_PSR2_CTL) &
> > EDP_PSR2_ENABLE);
> > + WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
> > return;
> > + }
> >
> > if (dev_priv->psr.psr2_enabled) {
> > val = I915_READ(EDP_PSR2_CTL);
> > @@ -680,32 +684,23 @@ static void
> > intel_psr_disable_source(struct intel_dp *intel_dp)
> > {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > + i915_reg_t psr_status;
> > + u32 psr_status_mask;
> >
> > - if (dev_priv->psr.active) {
> > - i915_reg_t psr_status;
> > - u32 psr_status_mask;
> > -
> > - intel_psr_exit(dev_priv);
> > + intel_psr_exit(dev_priv);
> >
> > - if (dev_priv->psr.psr2_enabled) {
> > - psr_status = EDP_PSR2_STATUS;
> > - psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
> > - } else {
> > - psr_status = EDP_PSR_STATUS;
> > - psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
> > - }
> > -
> > - /* Wait till PSR is idle */
> > - if (intel_wait_for_register(dev_priv,
> > - psr_status,
> > psr_status_mask, 0,
> > - 2000))
> > - DRM_ERROR("Timed out waiting for PSR Idle
> > State\n");
> > + if (dev_priv->psr.psr2_enabled) {
> > + psr_status = EDP_PSR2_STATUS;
> > + psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
> > } else {
> > - if (dev_priv->psr.psr2_enabled)
> > - WARN_ON(I915_READ(EDP_PSR2_CTL) &
> > EDP_PSR2_ENABLE);
> > - else
> > - WARN_ON(I915_READ(EDP_PSR_CTL) &
> > EDP_PSR_ENABLE);
> > + psr_status = EDP_PSR_STATUS;
> > + psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
> > }
> > +
> > + /* Wait till PSR is idle */
> > + if (intel_wait_for_register(dev_priv, psr_status,
> > psr_status_mask, 0,
> > + 2000))
> > + DRM_ERROR("Timed out waiting PSR idle state\n");
> > }
> >
> > static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> > --
> > 2.19.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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