The IIR register is a result of a AND operation between the mask
register and the actual interruption state so checking IIR before
unmask interruptions will never get any errors even if they exits.
Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5d1f53723388..21756e9a7523 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4086,8 +4086,8 @@ static int ironlake_irq_postinstall(struct drm_device
*dev)
}
if (IS_HASWELL(dev_priv)) {
- gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
+ gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
display_mask |= DE_EDP_PSR_INT_HSW;
}
@@ -4232,8 +4232,8 @@ static void gen8_de_irq_postinstall(struct
drm_i915_private *dev_priv)
else if (IS_BROADWELL(dev_priv))
de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
- gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
+ gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
for_each_pipe(dev_priv, pipe) {
dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
--
2.19.1
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