Also let's always consider next platform follows
the most recent one. Like we have done for transitioning
gen9 to gen10 and gent10 to gen11.
Let's use same approach for gen11+ and only introduce
changes later as needed.
Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
---
drivers/gpu/drm/i915/intel_cdclk.c | 6 +++---
drivers/gpu/drm/i915/intel_ddi.c | 18 +++++++++---------
drivers/gpu/drm/i915/intel_display.c | 8 ++++----
drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/intel_mocs.c | 3 +--
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
8 files changed, 24 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
b/drivers/gpu/drm/i915/intel_cdclk.c
index b315b70fd49c..915e2c93412b 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2572,7 +2572,7 @@ static int intel_compute_max_dotclk(struct
drm_i915_private *dev_priv)
*/
void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
{
- if (IS_ICELAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
if (dev_priv->cdclk.hw.ref == 24000)
dev_priv->max_cdclk_freq = 648000;
else
@@ -2801,12 +2801,12 @@ void intel_init_cdclk_hooks(struct drm_i915_private
*dev_priv)
dev_priv->display.set_cdclk = cnl_set_cdclk;
dev_priv->display.modeset_calc_cdclk =
cnl_modeset_calc_cdclk;
- } else if (IS_ICELAKE(dev_priv)) {
+ } else if (INTEL_GEN(dev_priv) >= 11) {
dev_priv->display.set_cdclk = icl_set_cdclk;
dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
}
- if (IS_ICELAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 11)
dev_priv->display.get_cdclk = icl_get_cdclk;
else if (IS_GEN10(dev_priv))
dev_priv->display.get_cdclk = cnl_get_cdclk;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cd627851f2a5..10b5314f266c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -915,7 +915,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private
*dev_priv, enum port por
level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
- if (IS_ICELAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
if (intel_port_is_combophy(dev_priv, port))
icl_get_combo_buf_trans(dev_priv, port,
INTEL_OUTPUT_HDMI, &n_entries);
@@ -1745,7 +1745,7 @@ static void intel_ddi_clock_get(struct intel_encoder
*encoder,
bxt_ddi_clock_get(encoder, pipe_config);
else if (IS_GEN10(dev_priv))
cnl_ddi_clock_get(encoder, pipe_config);
- else if (IS_ICELAKE(dev_priv))
+ else if (INTEL_GEN(dev_priv) >= 11)
icl_ddi_clock_get(encoder, pipe_config);
}
@@ -2241,7 +2241,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
enum port port = encoder->port;
int n_entries;
- if (IS_ICELAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
if (intel_port_is_combophy(dev_priv, port))
icl_get_combo_buf_trans(dev_priv, port, encoder->type,
&n_entries);
@@ -2716,7 +2716,7 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp)
struct intel_encoder *encoder = &dport->base;
int level = intel_ddi_dp_level(intel_dp);
- if (IS_ICELAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 11)
icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
level, encoder->type);
else if (IS_GEN10(dev_priv))
@@ -2833,7 +2833,7 @@ static void intel_ddi_clk_select(struct intel_encoder
*encoder,
mutex_lock(&dev_priv->dpll_lock);
- if (IS_ICELAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
if (!intel_port_is_combophy(dev_priv, port))
I915_WRITE(DDI_CLK_SEL(port),
icl_pll_to_ddi_pll_sel(encoder, crtc_state));
@@ -2875,7 +2875,7 @@ static void intel_ddi_clk_disable(struct intel_encoder
*encoder)
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = encoder->port;
- if (IS_ICELAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
if (!intel_port_is_combophy(dev_priv, port))
I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
} else if (IS_GEN10(dev_priv)) {
@@ -2917,7 +2917,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
icl_program_mg_dp_mode(intel_dp);
icl_disable_phy_clock_gating(dig_port);
- if (IS_ICELAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 11)
icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
level, encoder->type);
else if (IS_GEN10(dev_priv))
@@ -2956,7 +2956,7 @@ static void intel_ddi_pre_enable_hdmi(struct
intel_encoder *encoder,
intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
- if (IS_ICELAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 11)
icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
level, INTEL_OUTPUT_HDMI);
else if (IS_GEN10(dev_priv))
@@ -3375,7 +3375,7 @@ void intel_ddi_compute_min_voltage_level(struct
drm_i915_private *dev_priv,
{
if (IS_GEN10(dev_priv) && crtc_state->port_clock > 594000)
crtc_state->min_voltage_level = 2;
- else if (IS_ICELAKE(dev_priv) && crtc_state->port_clock > 594000)
+ else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
crtc_state->min_voltage_level = 1;
}
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 1abf79a4ee91..08d0cd802e48 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5932,7 +5932,7 @@ bool intel_port_is_combophy(struct drm_i915_private
*dev_priv, enum port port)
if (port == PORT_NONE)
return false;
- if (IS_ICELAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 11)
return port <= PORT_B;
return false;
@@ -5940,7 +5940,7 @@ bool intel_port_is_combophy(struct drm_i915_private
*dev_priv, enum port port)
bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
{
- if (IS_ICELAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 11)
return port >= PORT_C && port <= PORT_F;
return false;
@@ -9496,7 +9496,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc
*crtc,
port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
- if (IS_ICELAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 11)
icelake_get_ddi_pll(dev_priv, port, pipe_config);
else if (IS_GEN10(dev_priv))
cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
@@ -14049,7 +14049,7 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
if (intel_crt_present(dev_priv))
intel_crt_init(dev_priv);
- if (IS_ICELAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_C);
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index ae92dc97d5aa..b0ba775706b3 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -3200,7 +3200,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
const struct dpll_info *dpll_info;
int i;
- if (IS_ICELAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 11)
dpll_mgr = &icl_pll_mgr;
else if (IS_GEN10(dev_priv))
dpll_mgr = &cnl_pll_mgr;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 89d5e3984452..ab835370df19 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1919,7 +1919,7 @@ intel_hdmi_detect(struct drm_connector *connector, bool
force)
intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
- if (IS_ICELAKE(dev_priv) &&
+ if (INTEL_GEN(dev_priv) >= 11 &&
!intel_digital_port_connected(encoder))
goto out;
diff --git a/drivers/gpu/drm/i915/intel_mocs.c
b/drivers/gpu/drm/i915/intel_mocs.c
index 662eb087bb2e..d75b9a0c2bcc 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -178,8 +178,7 @@ static bool get_mocs_settings(struct drm_i915_private
*dev_priv,
{
bool result = false;
- if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv) ||
- IS_ICELAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEN9_BC(dev_priv)) {
table->size = ARRAY_SIZE(skylake_mocs_table);
table->table = skylake_mocs_table;
result = true;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7234b2272481..f4b7fd132173 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3612,8 +3612,8 @@ static bool skl_needs_memory_bw_wa(struct
intel_atomic_state *state)
static bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
- if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
- IS_GEN10(dev_priv) || IS_ICELAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 10 ||
+ IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
return true;
if (IS_SKYLAKE(dev_priv) &&
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 63f0b1c0bf77..1d7dd506708a 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3082,7 +3082,7 @@ int intel_power_domains_init(struct drm_i915_private
*dev_priv)
* The enabling order will be from lower to higher indexed wells,
* the disabling order is reversed.
*/
- if (IS_ICELAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
err = set_power_wells(power_domains, icl_power_wells);
} else if (IS_HASWELL(dev_priv)) {
err = set_power_wells(power_domains, hsw_power_wells);
@@ -3767,7 +3767,7 @@ void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv, bool resume)
power_domains->initializing = true;
- if (IS_ICELAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
icl_display_core_init(dev_priv, resume);
} else if (IS_GEN10(dev_priv)) {
cnl_display_core_init(dev_priv, resume);
@@ -3898,7 +3898,7 @@ void intel_power_domains_suspend(struct drm_i915_private
*dev_priv,
intel_power_domains_verify_state(dev_priv);
}
- if (IS_ICELAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 11)
icl_display_core_uninit(dev_priv);
else if (IS_GEN10(dev_priv))
cnl_display_core_uninit(dev_priv);
--
2.19.1
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