> -----Original Message-----
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
> Sent: Wednesday, September 26, 2018 7:52 PM
> To: Kulkarni, Vandita <vandita.kulka...@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nik...@intel.com>;
> Zanoni, Paulo R <paulo.r.zan...@intel.com>
> Subject: Re: [Intel-gfx] [RFC 3/3] drm/i915/icl: Calculate DPLL params for DSI
>
> On Thu, Sep 20, 2018 at 08:49:52AM +0000, Kulkarni, Vandita wrote:
> >
> >
> > > -----Original Message-----
> > > From: Ville Syrjälä <ville.syrj...@linux.intel.com>
> > > Sent: Friday, September 14, 2018 9:39 PM
> > > To: Kulkarni, Vandita <vandita.kulka...@intel.com>
> > > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani
> > > <jani.nik...@intel.com>; Zanoni, Paulo R <paulo.r.zan...@intel.com>
> > > Subject: Re: [Intel-gfx] [RFC 3/3] drm/i915/icl: Calculate DPLL
> > > params for DSI
> > >
> > > On Fri, Sep 14, 2018 at 12:24:14PM +0530, Vandita Kulkarni wrote:
> > > > From: Madhav Chauhan <madhav.chau...@intel.com>
> > > >
> > > > This patch calculate various DPLL dividers and parameters for DSI
> > > > encoder and adjust AFE clock for DSI. For DSI, 8x clock is AFE clock.
> > > >
> > > > v2: Extend haswell_crtc_compute_clock() for Gen11 DSI
> > > > v3: Rebase
> > > >
> > > > Signed-off-by: Madhav Chauhan <madhav.chau...@intel.com>
> > > > Signed-off-by: Vandita Kulkarni <vandita.kulka...@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/intel_display.c | 4 +++-
> > > > drivers/gpu/drm/i915/intel_dpll_mgr.c | 7 ++++++-
> > > > 2 files changed, 9 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > > b/drivers/gpu/drm/i915/intel_display.c
> > > > index 6928dcc..1a44c5e 100644
> > > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > > @@ -9238,10 +9238,12 @@ void hsw_disable_pc8(struct
> > > > drm_i915_private
> > > > *dev_priv) static int haswell_crtc_compute_clock(struct intel_crtc
> > > > *crtc,
> > > > struct intel_crtc_state
> > > > *crtc_state) {
> > > > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > > struct intel_atomic_state *state =
> > > > to_intel_atomic_state(crtc_state->base.state);
> > > >
> > > > - if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
> > > > + if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
> > > > + IS_ICELAKE(dev_priv)) {
> > > > struct intel_encoder *encoder =
> > > > intel_get_crtc_new_encoder(state, crtc_state);
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > > > b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > > > index 36ed155..5175e44 100644
> > > > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > > > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > > > @@ -22,6 +22,7 @@
> > > > */
> > > >
> > > > #include "intel_drv.h"
> > > > +#include "intel_dsi.h"
> > > >
> > > > /**
> > > > * DOC: Display PLLs
> > > > @@ -2532,7 +2533,11 @@ static bool icl_calc_dpll_state(struct
> > > intel_crtc_state *crtc_state,
> > > > ret = icl_calc_tbt_pll(dev_priv, clock, &pll_params);
> > > > else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> > > > ret = cnl_ddi_calculate_wrpll(clock, dev_priv,
> > > > &pll_params);
> > > > - else
> > > > + else if (encoder->type == INTEL_OUTPUT_DSI) {
> > > > + struct intel_dsi *intel_dsi =
> > > > enc_to_intel_dsi(&encoder->base);
> > > > + ret = cnl_ddi_calculate_wrpll(intel_dsi->bitrate_khz/5,
> > >
> > > Missing port_clock=whatever in compute config?
> > As per the spec I see that for mipi dsi on icl, 8x clock = AFE clock.
> > And 8x clock is calculated and stored already as pixel_clk * bpp /
> > lane_count Hence we are using already calculate 8x clock variable here
> > and divide by/5 because later in the function it gets multiplied by 5 for
> > afe
> clock.
> >
> > port_clock is assigned to pixel clock as I see.
>
> port_clock can basically be anything you want. It's really up to the encoder
> to
> define it. For DP it's the freq (1.62ghz, 2.7ghz, etc.), for HDMI it's the
> TMDS
> character rate, for SDVO it's the multiplied pixel clock, etc.
>
> I suppose that means that currently port_clock is the output from the dpll in
> pretty much all cases. Sticking to that same rule will make DSI look less
> special
> and thus easier to understand for everyone.
Thank you, I will assign this bitrate_khz (dsi_clk) to port_clock.
Regards,
Vandita
>
> > Please let me know if we have to use math around the port clock and pass
> > that
> value, than passing 8x clock.
> >
> > Thanks,
> > Vandita
> > >
> > > > + dev_priv, &pll_params);
> > > > + } else
> > > > ret = icl_calc_dp_combo_pll(dev_priv, clock,
> > > > &pll_params);
> > > >
> > > > if (!ret)
> > > > --
> > > > 1.9.1
> > > >
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
>
> --
> Ville Syrjälä
> Intel
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