On Wed, Jan 16, 2013 at 10:11:30AM -0800, Jesse Barnes wrote: > On Wed, 16 Jan 2013 19:59:03 +0200 > ville.syrj...@linux.intel.com wrote: > > > From: Ville Syrjälä <ville.syrj...@linux.intel.com> > > > > Fix up some copypaste errors in the PIPESTAT register for VLV. > > > > SPRITE0_FLIP_DONE_INT_EN_VLV is bit 22, not bit 26. > > > > SPRITE0_FLIPDONE_INT_STATUS_VLV is bit 14, not bit 15. > > > > Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 4 ++-- > > 1 files changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h > > index 36789bf..2745e7a 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -2674,7 +2674,7 @@ > > #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) > > #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) > > #define PIPE_DPST_EVENT_ENABLE (1UL<<23) > > -#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<26) > > +#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22) > > #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) > > #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) > > #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) > > @@ -2684,7 +2684,7 @@ > > #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) > > #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) > > #define SPRITE1_FLIPDONE_INT_STATUS_VLV (1UL<<15) > > -#define SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL<<15) > > +#define SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL<<14) > > #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) > > #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) > > #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) > > Reviewed-by: Jesse Barnes <jbar...@virtuousgeek.org>
Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
