This patch extends g2v notification to notify host GVT-g of
ppgtt update from guest, including alloc_4lvl, clear_4lv4 and
insert_4lvl. It uses shared page to pass the additional params.
This patch also add one new pvmmio level to control ppgtt update.
Use PVMMIO_PPGTT_UPDATE to control this level of pvmmio optimization.
Signed-off-by: Xiaolin Zhang <xiaolin.zh...@intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 36 ++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_params.h | 3 ++-
drivers/gpu/drm/i915/i915_pvinfo.h | 3 +++
3 files changed, 41 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index f6c7ab4..fe0cbd2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -990,6 +990,8 @@ static void gen8_ppgtt_clear_4lvl(struct i915_address_space
*vm,
struct i915_pml4 *pml4 = &ppgtt->pml4;
struct i915_page_directory_pointer *pdp;
unsigned int pml4e;
+ u64 orig_start = start;
+ u64 orig_length = length;
GEM_BUG_ON(!use_4lvl(vm));
@@ -1003,6 +1005,16 @@ static void gen8_ppgtt_clear_4lvl(struct
i915_address_space *vm,
free_pdp(vm, pdp);
}
+
+ if (PVMMIO_LEVEL_ENABLE(vm->i915, PVMMIO_PPGTT_UPDATE)) {
+ struct drm_i915_private *dev_priv = vm->i915;
+ struct pv_ppgtt_update *pv_ppgtt =
+ &dev_priv->shared_page->pv_ppgtt;
+ pv_ppgtt->pdp = px_dma(pml4);
+ pv_ppgtt->start = orig_start;
+ pv_ppgtt->length = orig_length;
+ I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_CLEAR);
+ }
}
static inline struct sgt_dma {
@@ -1244,6 +1256,18 @@ static void gen8_ppgtt_insert_4lvl(struct
i915_address_space *vm,
vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
}
+
+ if (PVMMIO_LEVEL_ENABLE(vm->i915, PVMMIO_PPGTT_UPDATE)) {
+ struct drm_i915_private *dev_priv = vm->i915;
+ struct pv_ppgtt_update *pv_ppgtt =
+ &dev_priv->shared_page->pv_ppgtt;
+ pv_ppgtt->pdp = px_dma(&ppgtt->pml4);
+ pv_ppgtt->start = vma->node.start;
+ pv_ppgtt->length = vma->node.size;
+ pv_ppgtt->cache_level = cache_level;
+ I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_INSERT);
+ }
+
}
static void gen8_free_page_tables(struct i915_address_space *vm,
@@ -1487,6 +1511,8 @@ static int gen8_ppgtt_alloc_4lvl(struct
i915_address_space *vm,
u64 from = start;
u32 pml4e;
int ret;
+ u64 orig_start = start;
+ u64 orig_length = length;
gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
if (pml4->pdps[pml4e] == vm->scratch_pdp) {
@@ -1503,6 +1529,16 @@ static int gen8_ppgtt_alloc_4lvl(struct
i915_address_space *vm,
goto unwind_pdp;
}
+ if (PVMMIO_LEVEL_ENABLE(vm->i915, PVMMIO_PPGTT_UPDATE)) {
+ struct drm_i915_private *dev_priv = vm->i915;
+ struct pv_ppgtt_update *pv_ppgtt =
+ &dev_priv->shared_page->pv_ppgtt;
+ pv_ppgtt->pdp = px_dma(pml4);
+ pv_ppgtt->start = orig_start;
+ pv_ppgtt->length = orig_length;
+ I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_ALLOC);
+ }
+
return 0;
unwind_pdp:
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index bfc30a0..f9fe6af 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -69,7 +69,8 @@
param(bool, enable_dp_mst, true) \
param(bool, enable_dpcd_backlight, false) \
param(bool, enable_gvt, false) \
- param(int, enable_pvmmio, PVMMIO_ELSP_SUBMIT | PVMMIO_MASTER_IRQ)
+ param(int, enable_pvmmio, PVMMIO_ELSP_SUBMIT | PVMMIO_MASTER_IRQ \
+ | PVMMIO_PPGTT_UPDATE)
#define MEMBER(T, member, ...) T member;
struct i915_params {
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h
b/drivers/gpu/drm/i915/i915_pvinfo.h
index 60183c7..39721f8 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -46,6 +46,9 @@ enum vgt_g2v_type {
VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
VGT_G2V_EXECLIST_CONTEXT_CREATE,
VGT_G2V_EXECLIST_CONTEXT_DESTROY,
+ VGT_G2V_PPGTT_L4_ALLOC,
+ VGT_G2V_PPGTT_L4_CLEAR,
+ VGT_G2V_PPGTT_L4_INSERT,
VGT_G2V_MAX,
};
--
1.8.3.1
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