From: Shobhit Kumar <shobhit.ku...@intel.com>
Added support for PSR entry counter and performance counters
Signed-off-by: Shobhit Kumar <shobhit.ku...@intel.com>
v2: Add psr enabled yes/no info
Signed-off-by: Rodrigo Vivi <rodrigo.v...@gmail.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 882a735..39513de 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1658,6 +1658,39 @@ static int i915_dpio_info(struct seq_file *m, void *data)
return 0;
}
+static int i915_edp_psr_status(struct seq_file *m, void *data)
+{
+ struct drm_info_node *node = (struct drm_info_node *) m->private;
+ struct drm_device *dev = node->minor->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ int count;
+ u32 psrctl, psrstat, psrperf;
+
+ /* Bit 31 gives the PSR enabled */
+ psrctl = I915_READ(EDP_PSR_CTL);
+ seq_printf(m, "PSR Enabled: %s\n",
+ yesno(psrctl & EDP_PSR_ENABLE));
+
+ /* Bits 19:16 gives the PSR entry count */
+ psrstat = I915_READ(EDP_PSR_STATUS_CTL);
+ count = ((psrstat >> 16) & 0xf);
+
+ /* Format the PSR Entry Count only for now.
+ * TBD: Other status information
+ */
+ seq_printf(m, "EDP_PSR_ENTRY_COUNT: %u\n", count);
+
+ /* Current PSR state */
+ count = ((psrstat >> 29) & 0x7);
+ seq_printf(m, "EDP_PSR_CURRENT_STATE: 0x%x\n", count);
+
+ /* Perfromance counter bit 23:0 */
+ psrperf = (I915_READ(EDP_PSR_PERF_CNT)) & 0xffffff;
+ seq_printf(m, "EDP_PSR_PERF_COUNTER: %u\n", psrperf);
+
+ return 0;
+}
+
static ssize_t
i915_wedged_read(struct file *filp,
char __user *ubuf,
@@ -2131,6 +2164,7 @@ static struct drm_info_list i915_debugfs_list[] = {
{"i915_swizzle_info", i915_swizzle_info, 0},
{"i915_ppgtt_info", i915_ppgtt_info, 0},
{"i915_dpio", i915_dpio_info, 0},
+ {"i915_edp_psr_status", i915_edp_psr_status, 0},
};
#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
--
1.7.11.7
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