>-----Original Message-----
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Singh, Gaurav K <gaurav.k.si...@intel.com>; Jani Nikula
><jani.nik...@linux.intel.com>; Ville Syrjala <ville.syrj...@linux.intel.com>;
>Srivatsa, Anusha <anusha.sriva...@intel.com>; Navare, Manasi D
><manasi.d.nav...@intel.com>
>Subject: [PATCH v2 23/23] drm/i915/dp: Disable DSC in source by disabling DSS
>CTL bits
>
>From: Gaurav K Singh <gaurav.k.si...@intel.com>
>
>1. Disable Left/right VDSC branch in DSS Ctrl reg
> depending on the number of VDSC engines being used 2. Disable joiner in DSS
>Ctrl reg
>
>v5 (From Manasi):
>* Add Disable PG2 for VDSC on eDP
>v4: (From Manasi)
>* Rebase on top of revised patches
>v3 (From Manasi):
>* Use old_crtc_state to find dsc params
>* Add a condition to disable only if
>dsc state compression is enabled
>* Use correct DSS CTL regs
>v2 (From Manasi):
>* Fix tons of compilation errors like undefined variables, incorrect use of
>macros
>and all dirty laundry
>
>Cc: Jani Nikula <jani.nik...@linux.intel.com>
>Cc: Ville Syrjala <ville.syrj...@linux.intel.com>
>Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
>Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>
>Signed-off-by: Gaurav K Singh <gaurav.k.si...@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.sriva...@intel.com>
>---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/intel_display.c | 13 ++++++++++++
> drivers/gpu/drm/i915/intel_vdsc.c | 38
>++++++++++++++++++++++++++++++++++++
> 3 files changed, 53 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 0ffc9a7..cb6a80a 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -3427,6 +3427,8 @@ extern bool intel_set_memory_cxsr(struct
>drm_i915_private *dev_priv,
> bool enable);
> extern void intel_dsc_enable(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state);
>+extern void intel_dsc_disable(struct intel_encoder *encoder,
>+ struct intel_crtc_state *crtc_state);
>
> int i915_reg_read_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file);
>diff --git a/drivers/gpu/drm/i915/intel_display.c
>b/drivers/gpu/drm/i915/intel_display.c
>index 6b1d151..2b0be6f 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -5829,6 +5829,9 @@ static void haswell_crtc_disable(struct intel_crtc_state
>*old_crtc_state,
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
>+ struct drm_connector_state *conn_state;
>+ struct drm_connector *conn;
>+ int i;
>
> intel_encoders_disable(crtc, old_crtc_state, old_state);
>
>@@ -5845,6 +5848,16 @@ static void haswell_crtc_disable(struct
>intel_crtc_state *old_crtc_state,
> if (!transcoder_is_dsi(cpu_transcoder))
> intel_ddi_disable_transcoder_func(old_crtc_state);
>
>+ for_each_new_connector_in_state(old_state, conn, conn_state, i) {
>+ struct intel_encoder *encoder =
>+ to_intel_encoder(conn_state->best_encoder);
>+
>+ if (conn_state->crtc != crtc)
>+ continue;
>+
>+ intel_dsc_disable(encoder, old_crtc_state);
>+ }
>+
> if (INTEL_GEN(dev_priv) >= 9)
> skylake_scaler_disable(intel_crtc);
> else
>diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
>b/drivers/gpu/drm/i915/intel_vdsc.c
>index 32da285..96f6f94 100644
>--- a/drivers/gpu/drm/i915/intel_vdsc.c
>+++ b/drivers/gpu/drm/i915/intel_vdsc.c
>@@ -1048,3 +1048,41 @@ void intel_dsc_enable(struct intel_encoder *encoder,
>
> return;
> }
>+
>+void intel_dsc_disable(struct intel_encoder *encoder,
>+ struct intel_crtc_state *old_crtc_state) {
>+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
>+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
>+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>+ enum pipe pipe = crtc->pipe;
>+ i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
>+ u32 dss_ctl1_val = 0, dss_ctl2_val = 0;
>+
>+ if (!old_crtc_state->dsc_params.compression_enable)
>+ return;
>+
>+ if (encoder->type == INTEL_OUTPUT_EDP) {
>+ dss_ctl1_reg = DSS_CTL1;
>+ dss_ctl2_reg = DSS_CTL2;
>+ } else {
>+ dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
>+ dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
>+ }
>+ dss_ctl1_val = I915_READ(dss_ctl1_reg);
>+ if (dss_ctl1_val & JOINER_ENABLE)
>+ dss_ctl1_val &= ~JOINER_ENABLE;
>+ I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
>+
>+ dss_ctl2_val = I915_READ(dss_ctl2_reg);
>+ if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||
>+ dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)
>+ dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
>+ RIGHT_BRANCH_VDSC_ENABLE);
>+ I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
>+
>+ /* Put the PG2 power well for VDSC on eDP */
>+ /* FIXME: Use VDSC power domain when its added */
>+ if (intel_dp_is_edp(intel_dp))
>+ intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); }
>--
>2.7.4
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