On Tue, Aug 28, 2018 at 12:54:13PM -0400, Jyoti Yadav wrote:
> From: Jyoti <jyoti.r.ya...@intel.com>
>
> This patch resolves the DMC FW loading issue.
> Earlier DMC FW package have only one DMC FW for one stepping. But as such
> there is no such restriction from Package side.
> For ICL icl_dmc_ver1_07.bin binary package has DMC FW for 2 steppings.
> So while reading the dmc_offset from package header, for 1st stepping offset
> used to come 0x0 and was working fine till now.
> But for second stepping and other steppings, offset is non zero numaber and is
> in dwords. So we need to convert into bytes to fetch correct DMC FW from
> correct place.
>
> v2 : Added check for DMC FW max size for various gen. (Imre Deak)
>
> Signed-off-by: Jyoti Yadav <jyoti.r.ya...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_csr.c | 24 ++++++++++++++++++++----
> 1 file changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_csr.c
> b/drivers/gpu/drm/i915/intel_csr.c
> index 1ec4f09..3f78a3e 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -55,7 +55,9 @@
> #define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
>
>
> -#define CSR_MAX_FW_SIZE 0x2FFF
> +#define BXT_CSR_MAX_FW_SIZE 0x2FFF
> +#define GLK_CNL_CSR_MAX_FW_SIZE 0x3FFF
> +#define ICL_CSR_MAX_FW_SIZE 0x5FFF
> #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
>
> struct intel_css_header {
> @@ -359,6 +361,8 @@ static uint32_t *parse_csr_fw(struct drm_i915_private
> *dev_priv,
> si->stepping);
> return NULL;
> }
> + /* Convert dmc_offset into number of bytes. By default it is in dwords*/
> + dmc_offset *= 4;
> readcount += dmc_offset;
>
> /* Extract dmc_header information. */
> @@ -391,9 +395,21 @@ static uint32_t *parse_csr_fw(struct drm_i915_private
> *dev_priv,
>
> /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
> nbytes = dmc_header->fw_size * 4;
> - if (nbytes > CSR_MAX_FW_SIZE) {
> - DRM_ERROR("DMC firmware too big (%u bytes)\n", nbytes);
> - return NULL;
> + if (IS_BROXTON(dev_priv)) {
> + if (nbytes > BXT_CSR_MAX_FW_SIZE) {
> + DRM_ERROR("DMC FW too big (%u bytes)\n", nbytes);
> + return NULL;
> + }
> + } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
> + if (nbytes > GLK_CNL_CSR_MAX_FW_SIZE) {
> + DRM_ERROR("DMC FW too big (%u bytes)\n", nbytes);
> + return NULL;
> + }
> + } else {
> + if (nbytes > ICL_CSR_MAX_FW_SIZE) {
> + DRM_ERROR("DMC FW too big (%u bytes)\n", nbytes);
> + return NULL;
> + }
To account for the rest of GEN9 platforms and avoid some duplication we'd
need something like the following (just using the GLK_CSR prefix, it's
enough to mark the first relevant platform):
+ if (INTEL_GEN(dev_priv) >= 11)
+ max_fw_size = ICL_CSR_MAX_FW_SIZE;
+ else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ max_fw_size = GLK_CSR_MAX_FW_SIZE;
+ else if (IS_GEN9(dev_priv))
+ max_fw_size = BXT_CSR_MAX_FW_SIZE;
+ else
+ MISSING_CASE(INTEL_REVID(dev_priv));
- if (nbytes > CSR_MAX_FW_SIZE) {
+ if (nbytes > max_fw_size) {
> }
> csr->dmc_fw_size = dmc_header->fw_size;
>
> --
> 1.9.1
>
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