On Wed, 2018-08-15 at 18:05 -0700, Dhinakaran Pandiyan wrote:
> gen8_de_irq_postinstall() wasn't masking the IRQ bit before passing
> the
> debug flag to psr_irq_control(). This check was missed when new debug
> bits
> were defined in 'commit c44301fce614 ("drm/i915: Allow control of
> PSR at
> runtime through debugfs, v6")'. Instead of ANDing the irq bit in all
> the
> callers, move it to the callee.
>
> Cc: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankho...@linux.intel.com> via IRC
"[8/20/18 11:58] <mlankhorst> or irc r-b"
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 2 +-
> drivers/gpu/drm/i915/intel_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_psr.c | 6 +++---
> 3 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index b2c9838442bc..8084e35b25c5 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -4048,7 +4048,7 @@ static int ironlake_irq_postinstall(struct
> drm_device *dev)
>
> if (IS_HASWELL(dev_priv)) {
> gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
> - intel_psr_irq_control(dev_priv, dev_priv->psr.debug
> & I915_PSR_DEBUG_IRQ);
> + intel_psr_irq_control(dev_priv, dev_priv-
> >psr.debug);
> display_mask |= DE_EDP_PSR_INT_HSW;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 7b984aefce98..bc1c53c5f4dd 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1944,7 +1944,7 @@ void intel_psr_flush(struct drm_i915_private
> *dev_priv,
> void intel_psr_init(struct drm_i915_private *dev_priv);
> void intel_psr_compute_config(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state);
> -void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool
> debug);
> +void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32
> debug);
> void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32
> psr_iir);
> void intel_psr_short_pulse(struct intel_dp *intel_dp);
> int intel_psr_wait_for_idle(const struct intel_crtc_state
> *new_crtc_state);
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 7560c65f50ad..df79020045a5 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -79,7 +79,7 @@ static bool intel_psr2_enabled(struct
> drm_i915_private *dev_priv,
> }
> }
>
> -void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool
> debug)
> +void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32
> debug)
> {
> u32 debug_mask, mask;
>
> @@ -100,7 +100,7 @@ void intel_psr_irq_control(struct
> drm_i915_private *dev_priv, bool debug)
> EDP_PSR_PRE_ENTRY(TRANSCODER_C);
> }
>
> - if (debug)
> + if (debug & I915_PSR_DEBUG_IRQ)
> mask |= debug_mask;
>
> I915_WRITE(EDP_PSR_IMR, ~mask);
> @@ -901,7 +901,7 @@ int intel_psr_set_debugfs_mode(struct
> drm_i915_private *dev_priv,
> if (crtc)
> dev_priv->psr.psr2_enabled =
> intel_psr2_enabled(dev_priv, crtc_state);
>
> - intel_psr_irq_control(dev_priv, dev_priv->psr.debug &
> I915_PSR_DEBUG_IRQ);
> + intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
>
> if (dev_priv->psr.prepared && enable)
> intel_psr_enable_locked(dev_priv, crtc_state);
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