On Tue, 18 Dec 2012 19:26:18 +0200, Mika Kuoppala
<mika.kuopp...@linux.intel.com> wrote:
> Hardware status page needs to have proper seqno set
> as our initial seqno can be arbitrary. If initial seqno is close
> to wrap boundary on init and i915_seqno_passed() (31bit space)
> refers to hw status page which contains zero, errorneous result
> will be returned.
>
> v2: clear mboxes and set hws page directly instead of going
> through rings. Suggested by Chris Wilson.
>
> v3: hws needs to be updated for all gens. Noticed by Chris
> Wilson.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=58230
> Signed-off-by: Mika Kuoppala <mika.kuopp...@intel.com>
> -int intel_ring_handle_seqno_wrap(struct intel_ring_buffer *ring)
> +void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
> {
> - int ret;
> + struct drm_i915_private *dev_priv = ring->dev->dev_private;
>
> BUG_ON(ring->outstanding_lazy_request);
>
> - if (INTEL_INFO(ring->dev)->gen < 6)
> - return 0;
> -
> - ret = __intel_ring_begin(ring, 6 * sizeof(uint32_t));
> - if (ret)
> - return ret;
> -
> - /* Leaving a stale, pre-wrap seqno behind in the mboxes will result in
> - * post-wrap semaphore waits completing immediately. Clear them. */
> - update_mboxes(ring, ring->signal_mbox[0]);
> - update_mboxes(ring, ring->signal_mbox[1]);
> - intel_ring_advance(ring);
> + if (INTEL_INFO(ring->dev)->gen >= 6) {
> + I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
> + I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
> + }
>
> - return 0;
> + intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
There's yet another complication here: not all gen use the HWS. Ironlake
uses a pipecontrol write to another page -- though in principle we could
write to the HWS instead.
Any one feel like that challenge?
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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