After
commit 2cd9a689e97b ("Refactor intel_display_set_init_power() logic")
it makes more sense to check the power domain/well refcounts after
enabling the power domains functionality. Before that it's guaranteed
that most power wells (in the INIT domain) will have a reference held,
so not an interesting state.
While at it also add the check after the init_hw/fini_hw, disable
and suspend/resume steps. The check is fast since the power well HW
state is cached.
v2:
- Add the state check to more spots. (Chris)
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Signed-off-by: Imre Deak <imre.d...@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 2 --
drivers/gpu/drm/i915/intel_drv.h | 1 -
drivers/gpu/drm/i915/intel_runtime_pm.c | 24 +++++++++++++++++++-----
3 files changed, 19 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 09d62b0c62cb..ad0f0e5389d9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15907,8 +15907,6 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
- intel_power_domains_verify_state(dev_priv);
-
intel_fbc_init_pipe_state(dev_priv);
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d0402051925b..529e72bcc5ef 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1966,7 +1966,6 @@ enum i915_drm_suspend_mode {
void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
enum i915_drm_suspend_mode);
void intel_power_domains_resume(struct drm_i915_private *dev_priv);
-void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6153d5be5cf6..813dc7684634 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3716,6 +3716,8 @@ static void vlv_cmnlane_wa(struct drm_i915_private
*dev_priv)
cmn->desc->ops->disable(dev_priv, cmn);
}
+static void intel_power_domains_verify_state(struct drm_i915_private
*dev_priv);
+
/**
* intel_power_domains_init_hw - initialize hardware power domain state
* @dev_priv: i915 device instance
@@ -3767,6 +3769,8 @@ void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv, bool resume)
intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
intel_power_domains_sync_hw(dev_priv);
power_domains->initializing = false;
+
+ intel_power_domains_verify_state(dev_priv);
}
/**
@@ -3788,6 +3792,8 @@ void intel_power_domains_fini_hw(struct drm_i915_private
*dev_priv)
/* Remove the refcount we took to keep power well support disabled. */
if (!i915_modparams.disable_power_well)
intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
+
+ intel_power_domains_verify_state(dev_priv);
}
/**
@@ -3805,6 +3811,8 @@ void intel_power_domains_fini_hw(struct drm_i915_private
*dev_priv)
void intel_power_domains_enable(struct drm_i915_private *dev_priv)
{
intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
+
+ intel_power_domains_verify_state(dev_priv);
}
/**
@@ -3817,6 +3825,8 @@ void intel_power_domains_enable(struct drm_i915_private
*dev_priv)
void intel_power_domains_disable(struct drm_i915_private *dev_priv)
{
intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
+
+ intel_power_domains_verify_state(dev_priv);
}
/**
@@ -3846,7 +3856,7 @@ void intel_power_domains_suspend(struct drm_i915_private
*dev_priv,
*/
if (!IS_GEN9_LP(dev_priv) && suspend_mode == I915_DRM_SUSPEND_IDLE &&
dev_priv->csr.dmc_payload != NULL)
- return;
+ goto verify_state;
/*
* Even if power well support was disabled we still want to disable
@@ -3865,6 +3875,10 @@ void intel_power_domains_suspend(struct drm_i915_private
*dev_priv,
bxt_display_core_uninit(dev_priv);
power_domains->display_core_suspended = true;
+
+verify_state:
+ intel_power_domains_verify_state(dev_priv);
+
}
/**
@@ -3884,11 +3898,11 @@ void intel_power_domains_resume(struct drm_i915_private
*dev_priv)
if (power_domains->display_core_suspended) {
intel_power_domains_init_hw(dev_priv, true);
power_domains->display_core_suspended = false;
-
- return;
+ } else {
+ intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
}
- intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
+ intel_power_domains_verify_state(dev_priv);
}
static void intel_power_domains_dump_info(struct drm_i915_private *dev_priv)
@@ -3919,7 +3933,7 @@ static void intel_power_domains_dump_info(struct
drm_i915_private *dev_priv)
* acquiring reference counts for any power wells in use and disabling the
* ones left on by BIOS but not required by any active output.
*/
-void intel_power_domains_verify_state(struct drm_i915_private *dev_priv)
+static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv)
{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
struct i915_power_well *power_well;
--
2.13.2
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