On Fri, Jul 27, 2018 at 12:36:47PM -0700, Lucas De Marchi wrote:
> Instead of defining all registers twice, define just a PCH_GPIO_BASE
> that has the same address as PCH_GPIO_A and use that to calculate all
> the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing
> the same thing.
>
> v2: Fix GMBUS registers to be relative to gpio base; create GPIO()
> macro to return a particular gpio address and move the enum out of
> i915_reg.h (suggested by Jani)
>
> v3: Move base offset inside the GPIO() macro so the GMBUS defines don't
> actually need to be changed (suggested by Daniel/Ville)
>
> v4: Move definition of i915_gpio to intel_display.h and remove
> GMBUS/GPIO handling from gvt since now they have their own
> defines.
>
> Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 3 ++-
> drivers/gpu/drm/i915/i915_reg.h | 24 +++++-------------------
> drivers/gpu/drm/i915/intel_display.h | 16 ++++++++++++++++
> drivers/gpu/drm/i915/intel_i2c.c | 16 ++++++++--------
> 4 files changed, 31 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0f49f9988dfa..19ad2a52ab04 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1604,7 +1604,8 @@ struct drm_i915_private {
> struct mutex gmbus_mutex;
>
> /**
> - * Base address of the gmbus and gpio block.
> + * Base address of where the gmbus and gpio blocks are located (either
> + * on PCH or on SoC for platforms without PCH).
> */
> uint32_t gpio_mmio_base;
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 07606677168c..827d442e1b12 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3168,18 +3168,9 @@ enum i915_power_well_id {
> /*
> * GPIO regs
> */
> -#define GPIOA _MMIO(0x5010)
> -#define GPIOB _MMIO(0x5014)
> -#define GPIOC _MMIO(0x5018)
> -#define GPIOD _MMIO(0x501c)
> -#define GPIOE _MMIO(0x5020)
> -#define GPIOF _MMIO(0x5024)
> -#define GPIOG _MMIO(0x5028)
> -#define GPIOH _MMIO(0x502c)
> -#define GPIOJ _MMIO(0x5034)
> -#define GPIOK _MMIO(0x5038)
> -#define GPIOL _MMIO(0x503C)
> -#define GPIOM _MMIO(0x5040)
> +#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
> + 4 * (gpio))
> +
> # define GPIO_CLOCK_DIR_MASK (1 << 0)
> # define GPIO_CLOCK_DIR_IN (0 << 1)
> # define GPIO_CLOCK_DIR_OUT (1 << 1)
> @@ -7574,6 +7565,8 @@ enum {
>
> /* PCH */
>
> +#define PCH_DISPLAY_BASE 0xc0000u
> +
> /* south display engine interrupt: IBX */
> #define SDE_AUDIO_POWER_D (1 << 27)
> #define SDE_AUDIO_POWER_C (1 << 26)
> @@ -7868,13 +7861,6 @@ enum {
> #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
> #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
>
> -#define PCH_GPIOA _MMIO(0xc5010)
> -#define PCH_GPIOB _MMIO(0xc5014)
> -#define PCH_GPIOC _MMIO(0xc5018)
> -#define PCH_GPIOD _MMIO(0xc501c)
> -#define PCH_GPIOE _MMIO(0xc5020)
> -#define PCH_GPIOF _MMIO(0xc5024)
> -
> #define _PCH_DPLL_A 0xc6014
> #define _PCH_DPLL_B 0xc6018
> #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
> diff --git a/drivers/gpu/drm/i915/intel_display.h
> b/drivers/gpu/drm/i915/intel_display.h
> index 0a79a46d5805..e7f49f107e57 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -25,6 +25,22 @@
> #ifndef _INTEL_DISPLAY_H_
> #define _INTEL_DISPLAY_H_
>
> +enum i915_gpio {
> + GPIOA,
> + GPIOB,
> + GPIOC,
> + GPIOD,
> + GPIOE,
> + GPIOF,
> + GPIOG,
> + GPIOH,
> + __GPIOI_UNUSED,
> + GPIOJ,
> + GPIOK,
> + GPIOL,
> + GPIOM,
> +};
> +
> enum pipe {
> INVALID_PIPE = -1,
>
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c
> b/drivers/gpu/drm/i915/intel_i2c.c
> index bef32b7c248e..33d87ab93fdd 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -37,7 +37,7 @@
>
> struct gmbus_pin {
> const char *name;
> - i915_reg_t reg;
> + enum i915_gpio gpio;
> };
>
> /* Map gmbus pin pairs to names and registers. */
> @@ -121,8 +121,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private
> *dev_priv,
> else
> size = ARRAY_SIZE(gmbus_pins);
>
> - return pin < size &&
> - i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
> + return pin < size && get_gmbus_pin(dev_priv, pin)->name;
> }
>
> /* Intel GPIO access functions */
> @@ -292,8 +291,7 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int
> pin)
>
> algo = &bus->bit_algo;
>
> - bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
> - i915_mmio_reg_offset(get_gmbus_pin(dev_priv,
> pin)->reg));
> + bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
> bus->adapter.algo_data = algo;
> algo->setsda = set_data;
> algo->setscl = set_clock;
> @@ -825,9 +823,11 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv)
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
> else if (!HAS_GMCH_DISPLAY(dev_priv))
> - dev_priv->gpio_mmio_base =
> - i915_mmio_reg_offset(PCH_GPIOA) -
> - i915_mmio_reg_offset(GPIOA);
> + /*
> + * Broxton uses the same PCH offsets for South Display Engine,
> + * even though it doesn't have a PCH.
> + */
> + dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
>
> mutex_init(&dev_priv->gmbus_mutex);
> init_waitqueue_head(&dev_priv->gmbus_wait_queue);
> --
> 2.17.1
>
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