From: "Srivatsa, Anusha" <anusha.sriva...@intel.com>
If the panel supports FEC, the driver has to
set the FEC_READY bit in the dpcd register:
FEC_CONFIGURATION.
This has to happen before link training.
v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
- change commit message. (Gaurav)
Cc: Gaurav K Singh <gaurav.k.si...@intel.com>
Cc: Jani Nikula <jani.nik...@linux.intel.com>
Cc: Ville Syrjala <ville.syrj...@linux.intel.com>
Cc: Manasi Navare <manasi.d.nav...@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 1 +
drivers/gpu/drm/i915/intel_dp.c | 17 +++++++++++++++++
drivers/gpu/drm/i915/intel_drv.h | 3 +++
3 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 5e8c891..9cdcc31 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2827,6 +2827,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
DP_DECOMPRESSION_EN);
+ intel_dp_sink_set_fec_ready(intel_dp, crtc_state, DP_FEC_READY);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index cb8b63e..5ef9005 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2948,6 +2948,23 @@ void intel_dp_sink_set_decompression_state(struct
intel_dp *intel_dp,
state == DP_DECOMPRESSION_EN ? "enable" :
"disable");
}
+void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ int state)
+{
+ int ret;
+
+ if (!crtc_state->dsc_params.compression_enable)
+ return;
+
+ if (intel_dp_is_edp(intel_dp))
+ return;
+
+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, state);
+ if (ret < 0)
+ DRM_DEBUG_KMS("Failed to get FEC enabled in sink\n");
+}
+
/* If the sink supports it, try to set the power state appropriately */
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
{
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0ecfacf..1ab9b20 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1696,6 +1696,9 @@ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int
mode);
void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
const struct intel_crtc_state
*crtc_state,
int state);
+void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ int state);
void intel_dp_encoder_reset(struct drm_encoder *encoder);
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
void intel_dp_encoder_destroy(struct drm_encoder *encoder);
--
2.7.4
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