Chris Wilson <ch...@chris-wilson.co.uk> writes:
> Make sure that the RPS IIR is completely clear on disabling so we should
> not get any more interrupts after idling. Since the IIR is shared with
> the guc, we have to be careful to only clobber RPS events.
>
> Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuopp...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 8 +++++---
> drivers/gpu/drm/i915/i915_reg.h | 6 ++++--
> 2 files changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index e37e3ec22a79..8084e35b25c5 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -478,7 +478,7 @@ void gen11_reset_rps_interrupts(struct drm_i915_private
> *dev_priv)
> void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
> {
> spin_lock_irq(&dev_priv->irq_lock);
> - gen6_reset_pm_iir(dev_priv, dev_priv->pm_rps_events);
> + gen6_reset_pm_iir(dev_priv, GEN6_PM_RPS_EVENTS);
> dev_priv->gt_pm.rps.pm_iir = 0;
> spin_unlock_irq(&dev_priv->irq_lock);
> }
> @@ -516,7 +516,7 @@ void gen6_disable_rps_interrupts(struct drm_i915_private
> *dev_priv)
>
> I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
>
> - gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
> + gen6_disable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
>
> spin_unlock_irq(&dev_priv->irq_lock);
> synchronize_irq(dev_priv->drm.irq);
> @@ -4778,7 +4778,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> /* WaGsvRC0ResidencyMethod:vlv */
> dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
> else
> - dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
> + dev_priv->pm_rps_events = (GEN6_PM_RP_UP_THRESHOLD |
> + GEN6_PM_RP_DOWN_THRESHOLD |
> + GEN6_PM_RP_DOWN_TIMEOUT);
>
> rps->pm_intrmsk_mbz = 0;
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e0f5999fff07..4b656f31fde9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8582,8 +8582,10 @@ enum {
> #define GEN6_PM_RP_DOWN_THRESHOLD (1 << 4)
> #define GEN6_PM_RP_UP_EI_EXPIRED (1 << 2)
> #define GEN6_PM_RP_DOWN_EI_EXPIRED (1 << 1)
> -#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
> - GEN6_PM_RP_DOWN_THRESHOLD | \
> +#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_EI_EXPIRED | \
> + GEN6_PM_RP_UP_THRESHOLD | \
> + GEN6_PM_RP_DOWN_EI_EXPIRED | \
> + GEN6_PM_RP_DOWN_THRESHOLD | \
> GEN6_PM_RP_DOWN_TIMEOUT)
GEN6_PM_RPS_MASK ?
Reviewed-by: Mika Kuoppala <mika.kuopp...@linux.intel.com>
>
> #define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4)
> --
> 2.18.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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