On Tue, Jul 17, 2018 at 02:11:01PM -0700, Anusha Srivatsa wrote:
> From: "Srivatsa, Anusha" <anusha.sriva...@intel.com>
>
> RC model has these parameters that correspond with each of
> 15 ranges of RC buffer threshold value in the RC model.
> The three elements are range_min_qp, range_max_qp and
> range_bpg_offset.
>
> Add the Rate Control range values for eDP/MIPI and DP case.
> The actual values are calculated usung a helper function.
> This patch adds the shifts to registers where the value will
> be written during atomic commit.
>
> v2:
> - Use _MMIO_PIPE() instead of _MMIO(_PICK()) (Manasi)
> - Combine shifts (Manasi)
>
> Cc: Jose Souza <jose.so...@intel.com>
> Cc: Jani Nikula <jani.nik...@intel.com>
> Cc: Ville Syrjala <ville.syrj...@linux.intel.com>
> Cc: Manasi Navare <manasi.d.nav...@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
Matches the spec, looks good to me.
Reviewed-by: Manasi Navare <manasi.d.nav...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 104
> ++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 104 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6fe2691..d763b6d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7678,6 +7678,110 @@ enum {
>
> #define SHOTPLUG_CTL_TC _MMIO(0xc4034)
> #define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4)
> +/* Icelake DSC Rate Control Range Parameter Registers */
> +#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
> +#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
> +#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
> +#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
> +#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) -
> PIPE_B, \
> +
> _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
> +
> _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
> +#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) -
> PIPE_B, \
> +
> _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
> +
> _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
> +#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) -
> PIPE_B, \
> +
> _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
> +
> _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
> +#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) -
> PIPE_B, \
> +
> _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
> +
> _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
> +#define RC_BPG_OFFSET_SHIFT 10
> +#define RC_MAX_QP_SHIFT 5
> +#define RC_MIN_QP_SHIFT 0
> +
> +#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
> +#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
> +#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
> +#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
> +#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) -
> PIPE_B, \
> +
> _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
> +
> _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
> +#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) -
> PIPE_B, \
> +
> _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
> +
> _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
> +#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) -
> PIPE_B, \
> +
> _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
> +
> _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
> +#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) -
> PIPE_B, \
> +
> _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
> +
> _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
> +
> +#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
> +#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
> +#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
> +#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
> +#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) -
> PIPE_B, \
> +
> _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
> +
> _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
> +#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) -
> PIPE_B, \
> +
> _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
> +
> _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
> +#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) -
> PIPE_B, \
> +
> _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
> +
> _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
> +#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) -
> PIPE_B, \
> +
> _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
> +
> _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
> +
> +#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
> +#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
> +#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
> +#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
> +#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) -
> PIPE_B, \
> +
> _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
> +
> _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
> +#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) -
> PIPE_B, \
> +
> _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
> +
> _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
> +#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) -
> PIPE_B, \
> +
> _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
> +
> _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
> +#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) -
> PIPE_B, \
> +
> _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
> +
> _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
> +
> #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
> #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
>
> --
> 2.7.4
>
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