This can be used to monitor the number of powergating transition
changes for a particular workload.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
drivers/gpu/drm/i915/intel_lrc.c | 16 +++++++++++++++-
drivers/gpu/drm/i915/intel_ringbuffer.h | 12 ++++++++++++
3 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 9f86e40f22a7..ab3ab80daf62 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -494,6 +494,7 @@ void intel_engine_setup_common(struct intel_engine_cs
*engine)
i915_timeline_init(engine->i915, &engine->timeline, engine->name);
memset(&engine->last_sseu, 0, sizeof(engine->last_sseu));
+ atomic_set(&engine->sseu_transitions, 0);
intel_engine_init_execlist(engine);
intel_engine_init_hangcheck(engine);
@@ -1428,6 +1429,8 @@ void intel_engine_dump(struct intel_engine_cs *engine,
hexdump(m, engine->status_page.page_addr, PAGE_SIZE);
drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine)));
+
+ drm_printf(m, "Powergating transitions: %u\n",
atomic_read(&engine->sseu_transitions));
}
static u8 user_class_map[] = {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0e93ad90d039..320b416482e1 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -520,6 +520,11 @@ static void port_assign(struct execlist_port *port, struct
i915_request *rq)
if (port_isset(port))
i915_request_put(port_request(port));
+ if (rq->sseu.value != rq->engine->last_sseu.value) {
+ rq->engine->last_sseu = rq->sseu;
+ atomic_inc(&rq->engine->sseu_transitions);
+ }
+
port_set(port, port_pack(i915_request_get(rq), port_count(port)));
}
@@ -779,6 +784,7 @@ execlists_cancel_port_requests(struct
intel_engine_execlists * const execlists)
while (num_ports-- && port_isset(port)) {
struct i915_request *rq = port_request(port);
+ bool completed = i915_request_completed(rq);
GEM_TRACE("%s:port%u global=%d (fence %llx:%d), (current %d)\n",
rq->engine->name,
@@ -789,10 +795,18 @@ execlists_cancel_port_requests(struct
intel_engine_execlists * const execlists)
GEM_BUG_ON(!execlists->active);
execlists_context_schedule_out(rq,
- i915_request_completed(rq) ?
+ completed ?
INTEL_CONTEXT_SCHEDULE_OUT :
INTEL_CONTEXT_SCHEDULE_PREEMPTED);
+ /*
+ * Update the last known sseu configuration to the first
+ * uncompleted request. Notice this works because we pop the
+ * requests out of the ports in reverse order.
+ */
+ if (!completed)
+ rq->engine->last_sseu = rq->sseu;
+
i915_request_put(rq);
memset(port, 0, sizeof(*port));
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 010750e8ee44..cc7e73730469 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -343,6 +343,18 @@ struct intel_engine_cs {
struct drm_i915_gem_object *default_state;
+ /**
+ * @last_sseu: The last SSEU configuration submitted to the
+ * hardware. Set to 0 if unknown.
+ */
+ union intel_sseu last_sseu;
+
+ /**
+ * @sseu_transitions: A counter of the number of powergating
+ * transition this engine has gone through.
+ */
+ atomic_t sseu_transitions;
+
atomic_t irq_count;
unsigned long irq_posted;
#define ENGINE_IRQ_BREADCRUMB 0
--
2.17.0
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