It is a common pattern to mark the tlbs dirty along with flushing
the writes. Introduce gen6_ppgtt_invalidate for this.
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Matthew Auld <matthew.a...@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuopp...@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 35 +++++++++++++++++++----------------
1 file changed, 19 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 2963d3d71729..b162617afe18 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -108,6 +108,21 @@
static int
i915_get_ggtt_vma_pages(struct i915_vma *vma);
+static void gen6_ppgtt_invalidate(struct i915_address_space * const vm)
+{
+ struct i915_hw_ppgtt * const ppgtt = i915_vm_to_ppgtt(vm);
+
+ /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
+ * the page table structures, we mark them dirty so that
+ * context switching/execlist queuing code takes extra steps
+ * to ensure that tlbs are flushed.
+ */
+ ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.i915)->ring_mask;
+
+ /* Flush write combining buffer */
+ wmb();
+}
+
static void gen6_ggtt_invalidate(struct drm_i915_private *dev_priv)
{
/* Flush write combining buffer */
@@ -814,15 +829,6 @@ static int gen8_mm_switch_4lvl(struct i915_hw_ppgtt *ppgtt,
return gen8_write_pdp(rq, 0, px_dma(&ppgtt->pml4));
}
-/* PDE TLBs are a pain to invalidate on GEN8+. When we modify
- * the page table structures, we mark them dirty so that
- * context switching/execlist queuing code takes extra steps
- * to ensure that tlbs are flushed.
- */
-static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
-{
- ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.i915)->ring_mask;
-}
/* Removes entries from a single page table, releasing it if it's empty.
* Caller can use the return value to update higher-level entries.
@@ -1398,7 +1404,7 @@ static int gen8_ppgtt_alloc_pdp(struct i915_address_space
*vm,
gen8_ppgtt_set_pdpe(vm, pdp, pd, pdpe);
GEM_BUG_ON(pdp->used_pdpes > i915_pdpes_per_pdp(vm));
- mark_tlbs_dirty(i915_vm_to_ppgtt(vm));
+ gen6_ppgtt_invalidate(vm);
}
ret = gen8_ppgtt_alloc_pd(vm, pd, start, length);
@@ -1724,8 +1730,7 @@ static void gen6_write_page_range(struct i915_hw_ppgtt
*ppgtt,
gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde)
gen6_write_pde(ppgtt, pde, pt);
- mark_tlbs_dirty(ppgtt);
- wmb();
+ gen6_ppgtt_invalidate(&ppgtt->base);
}
static inline u32 get_pd_offset(struct i915_hw_ppgtt *ppgtt)
@@ -1939,10 +1944,8 @@ static int gen6_alloc_va_range(struct i915_address_space
*vm,
}
}
- if (flush) {
- mark_tlbs_dirty(ppgtt);
- wmb();
- }
+ if (flush)
+ gen6_ppgtt_invalidate(vm);
return 0;
--
2.14.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
