Hi Matt, Thank you for the patch! Yet something to improve:
[auto build test ERROR on v4.16-rc4] [also build test ERROR on next-20180316] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/matthew-s-atwood-intel-com/drm-i915-make-edp-optimize-config/20180319-065307 config: i386-randconfig-a1-201811 (attached as .config) compiler: gcc-4.9 (Debian 4.9.4-2) 4.9.4 reproduce: # save the attached .config to linux build tree make ARCH=i386 All errors (new ones prefixed by >>): drivers/gpu/drm/i915/intel_dp.c: In function 'intel_dp_compute_config': >> drivers/gpu/drm/i915/intel_dp.c:1729:6: error: 'dpcd' undeclared (first use >> in this function) if(dpcd[DP_DPCD_REV] < DPCD_REV_14){ ^ drivers/gpu/drm/i915/intel_dp.c:1729:6: note: each undeclared identifier is reported only once for each function it appears in >> drivers/gpu/drm/i915/intel_dp.c:1729:26: error: 'DPCD_REV_14' undeclared >> (first use in this function) if(dpcd[DP_DPCD_REV] < DPCD_REV_14){ ^ vim +/dpcd +1729 drivers/gpu/drm/i915/intel_dp.c 1607 1608 bool 1609 intel_dp_compute_config(struct intel_encoder *encoder, 1610 struct intel_crtc_state *pipe_config, 1611 struct drm_connector_state *conn_state) 1612 { 1613 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1614 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1615 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1616 enum port port = encoder->port; 1617 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); 1618 struct intel_connector *intel_connector = intel_dp->attached_connector; 1619 struct intel_digital_connector_state *intel_conn_state = 1620 to_intel_digital_connector_state(conn_state); 1621 int lane_count, clock; 1622 int min_lane_count = 1; 1623 int max_lane_count = intel_dp_max_lane_count(intel_dp); 1624 /* Conveniently, the link BW constants become indices with a shift...*/ 1625 int min_clock = 0; 1626 int max_clock; 1627 int bpp, mode_rate; 1628 int link_avail, link_clock; 1629 int common_len; 1630 uint8_t link_bw, rate_select; 1631 bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc, 1632 DP_DPCD_QUIRK_LIMITED_M_N); 1633 1634 common_len = intel_dp_common_len_rate_limit(intel_dp, 1635 intel_dp->max_link_rate); 1636 1637 /* No common link rates between source and sink */ 1638 WARN_ON(common_len <= 0); 1639 1640 max_clock = common_len - 1; 1641 1642 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A) 1643 pipe_config->has_pch_encoder = true; 1644 1645 pipe_config->has_drrs = false; 1646 if (IS_G4X(dev_priv) || port == PORT_A) 1647 pipe_config->has_audio = false; 1648 else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 1649 pipe_config->has_audio = intel_dp->has_audio; 1650 else 1651 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON; 1652 1653 if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 1654 struct drm_display_mode *panel_mode = 1655 intel_connector->panel.alt_fixed_mode; 1656 struct drm_display_mode *req_mode = &pipe_config->base.mode; 1657 1658 if (!intel_edp_compare_alt_mode(req_mode, panel_mode)) 1659 panel_mode = intel_connector->panel.fixed_mode; 1660 1661 drm_mode_debug_printmodeline(panel_mode); 1662 1663 intel_fixed_panel_mode(panel_mode, adjusted_mode); 1664 1665 if (INTEL_GEN(dev_priv) >= 9) { 1666 int ret; 1667 ret = skl_update_scaler_crtc(pipe_config); 1668 if (ret) 1669 return ret; 1670 } 1671 1672 if (HAS_GMCH_DISPLAY(dev_priv)) 1673 intel_gmch_panel_fitting(intel_crtc, pipe_config, 1674 conn_state->scaling_mode); 1675 else 1676 intel_pch_panel_fitting(intel_crtc, pipe_config, 1677 conn_state->scaling_mode); 1678 } 1679 1680 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 1681 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 1682 return false; 1683 1684 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 1685 return false; 1686 1687 /* Use values requested by Compliance Test Request */ 1688 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { 1689 int index; 1690 1691 /* Validate the compliance test data since max values 1692 * might have changed due to link train fallback. 1693 */ 1694 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate, 1695 intel_dp->compliance.test_lane_count)) { 1696 index = intel_dp_rate_index(intel_dp->common_rates, 1697 intel_dp->num_common_rates, 1698 intel_dp->compliance.test_link_rate); 1699 if (index >= 0) 1700 min_clock = max_clock = index; 1701 min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count; 1702 } 1703 } 1704 DRM_DEBUG_KMS("DP link computation with max lane count %i " 1705 "max bw %d pixel clock %iKHz\n", 1706 max_lane_count, intel_dp->common_rates[max_clock], 1707 adjusted_mode->crtc_clock); 1708 1709 /* Walk through all bpp values. Luckily they're all nicely spaced with 2 1710 * bpc in between. */ 1711 bpp = intel_dp_compute_bpp(intel_dp, pipe_config); 1712 if (intel_dp_is_edp(intel_dp)) { 1713 1714 /* Get bpp from vbt only for panels that dont have bpp in edid */ 1715 if (intel_connector->base.display_info.bpc == 0 && 1716 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) { 1717 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", 1718 dev_priv->vbt.edp.bpp); 1719 bpp = dev_priv->vbt.edp.bpp; 1720 } 1721 1722 /* 1723 * Use the maximum clock and number of lanes the eDP panel 1724 * advertizes being capable of. The panels are generally 1725 * designed to support only a single clock and lane 1726 * configuration, and typically these values correspond to the 1727 * native resolution of the panel. 1728 */ > 1729 if(dpcd[DP_DPCD_REV] < DPCD_REV_14){ 1730 min_lane_count = max_lane_count; 1731 min_clock = max_clock; 1732 } 1733 } 1734 1735 for (; bpp >= 6*3; bpp -= 2*3) { 1736 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, 1737 bpp); 1738 1739 for (clock = min_clock; clock <= max_clock; clock++) { 1740 for (lane_count = min_lane_count; 1741 lane_count <= max_lane_count; 1742 lane_count <<= 1) { 1743 1744 link_clock = intel_dp->common_rates[clock]; 1745 link_avail = intel_dp_max_data_rate(link_clock, 1746 lane_count); 1747 1748 if (mode_rate <= link_avail) { 1749 goto found; 1750 } 1751 } 1752 } 1753 } 1754 1755 return false; 1756 1757 found: 1758 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 1759 /* 1760 * See: 1761 * CEA-861-E - 5.1 Default Encoding Parameters 1762 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 1763 */ 1764 pipe_config->limited_color_range = 1765 bpp != 18 && 1766 drm_default_rgb_quant_range(adjusted_mode) == 1767 HDMI_QUANTIZATION_RANGE_LIMITED; 1768 } else { 1769 pipe_config->limited_color_range = 1770 intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; 1771 } 1772 1773 pipe_config->lane_count = lane_count; 1774 1775 pipe_config->pipe_bpp = bpp; 1776 pipe_config->port_clock = intel_dp->common_rates[clock]; 1777 1778 intel_dp_compute_rate(intel_dp, pipe_config->port_clock, 1779 &link_bw, &rate_select); 1780 1781 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", 1782 link_bw, rate_select, pipe_config->lane_count, 1783 pipe_config->port_clock, bpp); 1784 DRM_DEBUG_KMS("DP link bw required %i available %i\n", 1785 mode_rate, link_avail); 1786 1787 intel_link_compute_m_n(bpp, lane_count, 1788 adjusted_mode->crtc_clock, 1789 pipe_config->port_clock, 1790 &pipe_config->dp_m_n, 1791 reduce_m_n); 1792 1793 if (intel_connector->panel.downclock_mode != NULL && 1794 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { 1795 pipe_config->has_drrs = true; 1796 intel_link_compute_m_n(bpp, lane_count, 1797 intel_connector->panel.downclock_mode->clock, 1798 pipe_config->port_clock, 1799 &pipe_config->dp_m2_n2, 1800 reduce_m_n); 1801 } 1802 1803 /* 1804 * DPLL0 VCO may need to be adjusted to get the correct 1805 * clock for eDP. This will affect cdclk as well. 1806 */ 1807 if (intel_dp_is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) { 1808 int vco; 1809 1810 switch (pipe_config->port_clock / 2) { 1811 case 108000: 1812 case 216000: 1813 vco = 8640000; 1814 break; 1815 default: 1816 vco = 8100000; 1817 break; 1818 } 1819 1820 to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco; 1821 } 1822 1823 if (!HAS_DDI(dev_priv)) 1824 intel_dp_set_clock(encoder, pipe_config); 1825 1826 intel_psr_compute_config(intel_dp, pipe_config); 1827 1828 return true; 1829 } 1830 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
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