On Thu, 25 Oct 2012 12:15:46 -0700, Jesse Barnes <jbar...@virtuousgeek.org> wrote: > So store into the scratch space of the HWS to make sure the invalidate > occurs. > > v2: use GTT address space for store, clean up #defines (Chris) > > Signed-off-by: Jesse Barnes <jbar...@virtuousgeek.org> > --- > @@ -1460,10 +1467,17 @@ static int blt_ring_flush(struct intel_ring_buffer > *ring, > return ret; > > cmd = MI_FLUSH_DW; > + /* > + * Bspec vol 1c.3 - blitter engine command streamer: > + * "If ENABLED, all TLBs will be invalidated once the flush > + * operation is complete. This bit is only valid when the > + * Post-Sync Operation field is a value of 1h or 3h." > + */ > if (invalidate & I915_GEM_DOMAIN_RENDER) > - cmd |= MI_INVALIDATE_TLB; > + cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | > + MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_OP_STOREDW; > intel_ring_emit(ring, cmd); > - intel_ring_emit(ring, 0); > + intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_INDEX | MI_FLUSH_DW_USE_GTT);
s/SCRATCH_INDEX/SCRATCH_ADDR/ -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
