Transition WM exist on gen9 but it is not recommended.
Let's make this decision clear and call rename the
function from "skl_" to "cnl_" so we don't have false
expectations that transitions should be running on CNL.
Also we remove two redundant checks inside this function
if (gen <= 9) exit
if (gen >= 10)...
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Mahesh Kumar <mahesh1.ku...@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 20 ++++++++------------
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a88f0f213604..1c2f824b1238 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4690,7 +4690,7 @@ skl_compute_linetime_wm(struct intel_crtc_state *cstate)
return linetime_wm;
}
-static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
+static void cnl_compute_transition_wm(struct intel_crtc_state *cstate,
struct skl_wm_params *wp,
struct skl_wm_level *wm_l0,
uint16_t ddb_allocation,
@@ -4698,25 +4698,17 @@ static void skl_compute_transition_wm(struct
intel_crtc_state *cstate,
{
struct drm_device *dev = cstate->base.crtc->dev;
const struct drm_i915_private *dev_priv = to_i915(dev);
- uint16_t trans_min, trans_y_tile_min;
+ uint16_t trans_min = 4, trans_y_tile_min;
const uint16_t trans_amount = 10; /* This is configurable amount */
uint16_t trans_offset_b, res_blocks;
if (!cstate->base.active)
goto exit;
- /* Transition WM are not recommended by HW team for GEN9 */
- if (INTEL_GEN(dev_priv) <= 9)
- goto exit;
-
/* Transition WM don't make any sense if ipc is disabled */
if (!dev_priv->ipc_enabled)
goto exit;
- trans_min = 0;
- if (INTEL_GEN(dev_priv) >= 10)
- trans_min = 4;
-
trans_offset_b = trans_min + trans_amount;
if (wp->y_tiled) {
@@ -4784,8 +4776,12 @@ static int skl_build_pipe_wm(struct intel_crtc_state
*cstate,
intel_pstate, &wm_params, wm);
if (ret)
return ret;
- skl_compute_transition_wm(cstate, &wm_params, &wm->wm[0],
- ddb_blocks, &wm->trans_wm);
+
+ /* Transition WM are not recommended by HW team for GEN9 */
+ if (INTEL_GEN(dev_priv) >= 10)
+ cnl_compute_transition_wm(cstate, &wm_params,
+ &wm->wm[0], ddb_blocks,
+ &wm->trans_wm);
}
pipe_wm->linetime = skl_compute_linetime_wm(cstate);
--
2.13.6
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