Implements the HDMI adapatation specific HDCP2.2 operations
intel_hdcp2_shim.
Basically these are DDC read and write for authenticating through
HDCP2.2 messages.
Signed-off-by: Ramalingam C <ramalinga...@intel.com>
---
drivers/gpu/drm/i915/intel_hdmi.c | 206 ++++++++++++++++++++++++++++++++++++++
1 file changed, 206 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 23986c02dd41..ac5a69f5aeaa 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1119,6 +1119,212 @@ static const struct intel_hdcp_shim
intel_hdmi_hdcp_shim = {
.check_link = intel_hdmi_hdcp_check_link,
};
+static
+int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
+ union hdcp2_hdmi_rx_status *rx_status)
+{
+ return intel_hdmi_hdcp_read(intel_dig_port,
+ HDMI_HDCP_2_2_REG_RXSTATUS_OFFSET,
+ rx_status,
+ sizeof(union hdcp2_hdmi_rx_status));
+}
+
+static inline
+int intel_hdmi_hdcp2_timeout_for_msg(uint8_t msg_id, bool is_paired)
+{
+ int timeout = -EINVAL;
+
+ switch (msg_id) {
+ case AKE_SEND_CERT:
+ timeout = HDCP_2_2_CERT_TIMEOUT;
+ break;
+ case AKE_SEND_HPRIME:
+ if (is_paired)
+ timeout = HDCP_2_2_HPRIME_PAIRED_TIMEOUT;
+ else
+ timeout = HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT;
+ break;
+ case AKE_SEND_PARING_INFO:
+ timeout = HDCP_2_2_PAIRING_TIMEOUT;
+ break;
+ case LC_SEND_LPRIME:
+ timeout = HDCP_2_2_HDMI_LPRIME_TIMEOUT;
+ break;
+ case REP_SEND_RECVID_LIST:
+ timeout = HDCP_2_2_RECVID_LIST_TIMEOUT;
+ break;
+ case REP_STREAM_READY:
+ timeout = HDCP_2_2_STREAM_READY_TIMEOUT;
+ break;
+ default:
+ DRM_ERROR("Unsupported msg_id: %d\n", (int)msg_id);
+ }
+ return timeout;
+}
+
+static inline
+int hdcp2_detect_msg_availability(struct intel_digital_port
*intel_digital_port,
+ uint8_t msg_id, bool *msg_ready,
+ ssize_t *msg_sz)
+{
+ union hdcp2_hdmi_rx_status rx_status;
+ int ret;
+
+ ret = intel_hdmi_hdcp2_read_rx_status(intel_digital_port, &rx_status);
+ if (ret < 0) {
+ DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret);
+ return ret;
+ }
+
+ /* Big endian to Little endian */
+ rx_status.val = __swab16(rx_status.val);
+ *msg_sz = rx_status.fields.msg_sz_hi << 8 | rx_status.fields.msg_sz_lo;
+
+ if (msg_id == REP_SEND_RECVID_LIST)
+ *msg_ready = (rx_status.fields.ready && msg_sz);
+ else
+ *msg_ready = *msg_sz;
+
+ return 0;
+}
+
+/**
+ * intel_hdmi_hdcp2_wait_for_msg: Detects the hdmi hdcp2.2 msg availability
+ * @hdcp: hdcp structure
+ * @msg_id: Message ID for which we are waiting
+ *
+ * Detects the HDMI HDCP2.2 Message availability
+ *
+ * Returns -ETIMEOUT in case of timeout, Message Size on success
+ */
+static ssize_t
+intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
+ uint8_t msg_id, bool paired)
+{
+ bool msg_ready = false;
+ int timeout, ret;
+ ssize_t msg_sz;
+
+ timeout = intel_hdmi_hdcp2_timeout_for_msg(msg_id, paired);
+ if (timeout < 0)
+ return timeout;
+
+ ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port,
+ msg_id, &msg_ready, &msg_sz),
+ !ret && msg_ready && msg_sz, timeout * 1000,
+ 1000, 5 * 1000);
+ if (ret)
+ DRM_ERROR("msg_id: %d, ret: %d, timeout: %d\n",
+ msg_id, ret, timeout);
+ return ret ? ret : msg_sz;
+}
+
+static
+int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
+ void *buf, size_t size)
+{
+ unsigned int offset;
+
+ offset = HDMI_HDCP_2_2_REG_WR_MSG_OFFSET;
+ return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size);
+}
+
+static
+int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
+ uint8_t msg_id, void *buf, size_t size)
+{
+ struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
+ struct intel_hdcp *hdcp = hdmi->attached_connector->hdcp;
+ struct drm_i915_private *dev_priv;
+ struct i2c_adapter *adapter;
+ unsigned int offset;
+ ssize_t ret;
+
+ ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id,
+ hdcp->is_paired);
+ if (ret < 0)
+ return ret;
+
+ /*
+ * Available msg size should be equal to or lesser than the
+ * available buffer.
+ */
+ if (ret > size) {
+ DRM_DEBUG_KMS("msg_sz(%d) is more than exp size(%d)\n",
+ (int)ret, (int)size);
+ return -1;
+ }
+
+ offset = HDMI_HDCP_2_2_REG_RD_MSG_OFFSET;
+
+ if (msg_id == AKE_SEND_CERT) {
+ dev_priv = intel_dig_port->base.base.dev->dev_private;
+ adapter = intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
+
+ ret = intel_gmbus_burst_read(adapter, offset, buf, ret);
+ } else {
+ ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret);
+ }
+
+ if (ret)
+ DRM_DEBUG_KMS("msg_id: %d, ret: %d\n", msg_id, (int)ret);
+ return ret;
+}
+
+static
+int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
+{
+ union hdcp2_hdmi_rx_status rx_status;
+ int ret;
+
+ ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, &rx_status);
+ if (ret)
+ return ret;
+
+ /*
+ * Re-auth request and Link Integrity Failures are represented by
+ * same bit. i.e reauth_req.
+ */
+ if (rx_status.fields.reauth_req)
+ ret = DRM_HDCP_REAUTH_REQUEST;
+ else if (rx_status.fields.ready)
+ ret = DRM_HDCP_TOPOLOGY_CHANGE;
+
+ return ret;
+}
+
+static
+int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port,
+ bool *capable)
+{
+ uint8_t hdcp2version;
+ int ret;
+
+ *capable = false;
+ ret = intel_hdmi_hdcp_read(intel_dig_port, HDMI_HDCP_2_2_REG_VER_OFFSET,
+ &hdcp2version, sizeof(hdcp2version));
+ if (!ret)
+ if (hdcp2version & HDMI_HDCP_2_2_SUPPORT_MASK)
+ *capable = true;
+
+ return ret;
+}
+
+static
+enum hdcp_protocol intel_hdmi_hdcp2_protocol(void)
+{
+ return HDCP_PROTOCOL_HDMI;
+}
+
+static const struct intel_hdcp2_shim intel_hdmi_hdcp2_shim = {
+ .write_msg = intel_hdmi_hdcp2_write_msg,
+ .read_msg = intel_hdmi_hdcp2_read_msg,
+ .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
+ .check_link = intel_hdmi_hdcp2_check_link,
+ .hdcp_capable = intel_hdmi_hdcp2_capable,
+ .hdcp_protocol = intel_hdmi_hdcp2_protocol,
+};
+
static void intel_hdmi_prepare(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
--
2.7.4
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