On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
> Eventhough Valleyview display block is derived from Cantiga, VLV
> supports eDP. So, added eDP checks in i9xx_crtc_mode_set path.
>
> v2: use different DPIO_DIVISOR values for VGA, DP and eDP
> v3: fix DPIO value calculation to use same values for all display
> interfaces
>
> Signed-off-by: Gajanan Bhat <gajanan.b...@intel.com>
> Signed-off-by: Vijay Purushothaman <vijay.a.purushotha...@intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 6 ++++++
> drivers/gpu/drm/i915/intel_dp.c | 13 ++++++++-----
> 2 files changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index a8a81d1..aee6151 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4405,6 +4405,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
> }
> }
>
> + if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
> + pipeconf |= PIPECONF_BPP_6 |
> + PIPECONF_ENABLE |
> + I965_PIPECONF_ACTIVE;
> + }
No.
Jani Nikula and me just figured out that we have a giant mess with 6bpc
dithering on DP outputs, but unconditionally enabling 6bpc on vlv eDP only
papers over issues.
> +
> DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
> drm_mode_debug_printmodeline(mode);
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index c111c3f..af57027 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -885,7 +885,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct
> drm_display_mode *mode,
>
> /* Split out the IBX/CPU vs CPT settings */
>
> - if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
> + if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
> if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> intel_dp->DP |= DP_SYNC_HS_HIGH;
> if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
> @@ -1474,7 +1474,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp,
> uint8_t voltage_swing)
> {
> struct drm_device *dev = intel_dp->base.base.dev;
>
> - if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
> + if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> case DP_TRAIN_VOLTAGE_SWING_400:
> return DP_TRAIN_PRE_EMPHASIS_6;
> @@ -1773,7 +1773,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
> uint32_t signal_levels;
>
>
> - if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
> + if (IS_GEN7(dev) && is_cpu_edp(intel_dp) &&
> !IS_VALLEYVIEW(dev)) {
> signal_levels =
> intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
> DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) |
> signal_levels;
> } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
> @@ -1859,7 +1859,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
> break;
> }
>
> - if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
> + if (IS_GEN7(dev) && is_cpu_edp(intel_dp) &&
> !IS_VALLEYVIEW(dev)) {
> signal_levels =
> intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
> DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) |
> signal_levels;
> } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
> @@ -2471,7 +2471,10 @@ intel_dp_init(struct drm_device *dev, int output_reg,
> enum port port)
> if (intel_dpd_is_edp(dev))
> intel_dp->is_pch_edp = true;
>
> - if (output_reg == DP_A || is_pch_edp(intel_dp)) {
> + if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
> + type = DRM_MODE_CONNECTOR_eDP;
> + intel_encoder->type = INTEL_OUTPUT_EDP;
You need to be a notch more careful, since since
commit cb0953d734348e8862d6d7edc666cfb3bf6d8fae
Author: Adam Jackson <a...@redhat.com>
Date: Fri Jul 16 14:46:29 2010 -0400
drm/i915: Initialize LVDS and eDP outputs before anything else
We initialize built-in panels before external outputs. Hence you need to
adjust intel_setup_outputs for vlv eDP, too, so that the eDP output comes
first. A bit a mess, I know.
Cheers, Daniel
> + } else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
> type = DRM_MODE_CONNECTOR_eDP;
> intel_encoder->type = INTEL_OUTPUT_EDP;
> } else {
> --
> 1.7.9.5
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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