On 9 October 2017 at 13:07, Ville Syrjälä <ville.syrj...@linux.intel.com> wrote: > On Mon, Oct 02, 2017 at 03:31:44PM +0300, Joonas Lahtinen wrote: >> On Fri, 2017-09-29 at 17:10 +0100, Matthew Auld wrote: >> > When SW enables the use of 2M/1G pages, it must disable the GTT cache. >> > >> > v2: don't disable for Cherryview which doesn't even support 48b PPGTT! >> > >> > v3: explicitly check that the system does support 2M/1G pages >> > >> > Signed-off-by: Matthew Auld <matthew.a...@intel.com> >> > Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> >> > Cc: Chris Wilson <ch...@chris-wilson.co.uk> >> > Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> >> > Reviewed-by: Mika Kuoppala <mika.kuopp...@linux.intel.com> >> >> <SNIP> >> >> > @@ -8483,10 +8483,11 @@ static void bdw_init_clock_gating(struct >> > drm_i915_private *dev_priv) >> > >> > /* >> > * WaGttCachingOffByDefault:bdw >> > - * GTT cache may not work with big pages, so if those >> > - * are ever enabled GTT cache may need to be disabled. >> > + * The GTT cache must be disabled if the system is using 2M/1G pages. >> > */ >> > - I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); >> > + I915_WRITE(HSW_GTT_CACHE_EN, >> > + HAS_PAGE_SIZES(dev_priv, I915_GTT_PAGE_SIZE_2M) ? 0 : >> > + GTT_CACHE_EN_ALL); >> >> Umm, this is mixing a known W/A with decision logic. >> >> bool can_use_gtt_cache = !HAS_PAGE_SIZES(dev_priv, >> I915_GTT_PAGE_SIZE_2M); >> >> /* WaGttCachingOffByDefault:bdw */ >> I915_WRITE(HSW_GTT_CACHE_EN, can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0); >> >> The big question is that if everyone else has GTT caching enabled by >> default, should not we actively be disabling it on other code paths? > > HSW has it enabled by default. BDW B0 disabled it by default, even > though the spec seems to suggest that the big pages vs. GTT cache issue > may have been fixed properly already on BDW. Did anyone actually test > whether big pages work with the GTT cache enabled?
Back when I was originally testing 2M pages on my BDW machine, I was seeing lots of nasty visual corruption, and so only stumbled on disabling the GTT cache after. The bit in the spec which caught my eye at the time[1]. It might be worth making sure the same holds true for SKL+.... [1] https://gfxspecs.intel.com/Predator/Home/Index/423 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
