On Tue, 2017-10-03 at 00:06 -0700, Rodrigo Vivi wrote:
> According to spec "If voltage is set too low,
> it will break functionality. If voltage is set too high,
> it will waste power."
>
> So, let's prefer the waste of power instead of breaking
> functionality.
>
> But also the logic of deciding the level on spec
> tells "Else, use level 2."
> So, default is actually "2", not "0".
The spec also says
"If CD clock = 168 MHz AND DDI clock ≤ 594 MHz, use level 0.
Else If CD clock = 336 MHz AND DDI clock ≤ 594 MHz, use level 1.
Else, use level 2."
Should we add check for DDI clock rate as well here?
>
> v2: Rebase moving it up to avoid some temporary code
> duplication.
>
> Cc: Mika Kahola <mika.kah...@intel.com>
> Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_cdclk.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> b/drivers/gpu/drm/i915/intel_cdclk.c
> index af8411c2a6b9..7e9c4444c844 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1562,15 +1562,15 @@ static void cnl_set_cdclk(struct
> drm_i915_private *dev_priv,
> }
>
> switch (cdclk) {
> - case 528000:
> - pcu_ack = 2;
> + case 168000:
> + pcu_ack = 0;
> break;
> case 336000:
> pcu_ack = 1;
> break;
> - case 168000:
> + case 528000:
> default:
> - pcu_ack = 0;
> + pcu_ack = 2;
> break;
> }
>
--
Mika Kahola - Intel OTC
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