On Thu, Sep 28, 2017 at 11:18:27AM +0100, Chris Wilson wrote: > Quoting Imre Deak (2017-09-28 11:06:24) > > Only init / reset the display interrupts during power well enabling / > > disabling if the i915 interrupts are enabled. So far we did the > > init / reset during driver loading / resuming too, where > > initialization / enabling of the i915 interrupts happens only at a later > > point. This didn't cause a problem due to GEN8_MASTER_IRQ_CONTROL being > > cleared, but triggered gen3_assert_iir_is_zero() in GEN8_IRQ_INIT_NDX(). > > > > References: https://bugs.freedesktop.org/show_bug.cgi?id=102988 > > Cc: Chris Wilson <ch...@chris-wilson.co.uk> > > Signed-off-by: Imre Deak <imre.d...@intel.com> > > Patch makes sense, so > Reviewed-by: Chris Wilson <ch...@chris-wilson.co.uk>
Thanks. > > There's an irq powerwell! When is it taken? We don't take it for GT as > far as I am aware (we should for execlists plus whenever we enable the > user interrupt). Should we? Only the display interrupt registers have a power well that we toggle from the driver (display power well/power well 2). The rest of interrupt regs including the GT ones are backed by a power well that the HW/DMC FW toggles automatically (always-on power well/power well 0). So no need to take it explicitly; there is the slow-down problem where the context restore during such enabling by DMC adds overhead, which will be solved by Tvrtko's WA. --Imre > -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
