On Fri, 10 Aug 2012 11:07:47 +0100, Chris Wilson <ch...@chris-wilson.co.uk> wrote: > On Fri, 10 Aug 2012 12:57:59 +0300, Jani Nikula <jani.nik...@linux.intel.com> > wrote: > > On Fri, 10 Aug 2012, Chris Wilson <ch...@chris-wilson.co.uk> wrote: > > > When invalidating the TLBs it is documentated as requiring a post-sync > > > write. Failure to do so seems to result in a GPU hang. > > > > > > Exposure to this hang on IVB seems to be a result of removing the extra > > > stalls required for SNB pipecontrol workarounds: > > > > Hi Chris, AFAICT TLB invalidate requires PIPE_CONTROL_CS_STALL set per > > the spec. I can't find a mention of the post-sync write, though. Could > > you double check, please?
To be clear, the w/a is mentioned for DevGT-A (but presumably still required): For all PIPE_CONTROLs that *only* have RO cache invalidation, software must set the post-sync operation field to something other than 0 -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
