Em Seg, 2017-07-17 às 15:05 -0700, Manasi Navare escreveu:
> The condition for setting the Loadgen Select bit of
> PORT_TX_DW4 register during DDI Vswing Sequence should be
> Bit rate <=6 GHz whereas the existing code checks only
> Bit Rate < 6GHz. This patch fixes this condition.
> While at it also remove the redundant paranthesis.
>
> Fixes: cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing
> sequence.")
> Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index efb1358..f4fbb39 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2010,8 +2010,8 @@ static void cnl_ddi_vswing_sequence(struct
> intel_encoder *encoder, u32 level)
> val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
> val &= ~LOADGEN_SELECT;
>
> - if (((rate < 600000) && (width == 4) && (ln >=
> 1)) ||
> - ((rate < 600000) && (width < 4) && ((ln == 1) ||
> (ln == 2)))) {
> + if ((rate <= 600000 && width == 4 && ln >= 1) ||
> + (rate <= 600000 && width < 4 && (ln == 1 || ln
> == 2))) {
> val |= LOADGEN_SELECT;
> }
> I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
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