On ma, 2017-06-05 at 11:26 +0100, Chris Wilson wrote:
> Enabling the interrupt for the signaler takes a finite amount of time (a
> few microseconds) during which it is possible for the request to
> complete. Check afterwards and skip adding the request to the signal
> rbtree if it complete.
>
> Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
<SNIP>
> +++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
> @@ -714,27 +714,33 @@ void intel_engine_enable_signaling(struct
> drm_i915_gem_request *request,
> + if (!__i915_gem_request_completed(request, seqno)) {
> + /* Now insert ourselves into the retirement ordered list of
> + * signals on this engine. We track the oldest seqno as that
> + * will be the first signal to complete.
> + */
> + parent = NULL;
> + first = true;
> + p = &b->signals.rb_node;
These variables could be more tightly scoped now.
> + while (*p) {
> + parent = *p;
> + if (i915_seqno_passed(seqno,
> +
> to_signaler(parent)->signaling.wait.seqno)) {
Alignment incorrect.
Reviewed-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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