hmm... didn't considered 2 pixels per clock.
thanks.
Reviewed-by: Mahesh Kumar <mahesh1.ku...@intel.com>
On Thursday 01 June 2017 04:04 PM, Maarten Lankhorst wrote:
Seems that GLK has a dotclock that's twice the display clock.
skl_max_scale checks for IS_GEMINILAKE, so perform the same check here.
While at it, change the DRM_ERROR to DEBUG_KMS.
Fixes: 73b0ca8ec76d ("drm/i915/skl+: consider max supported plane pixel
rate while scaling")
Cc: Mahesh Kumar <mahesh1.ku...@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2042f6512e6e..88c8a3511e24 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4122,7 +4122,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc
*intel_crtc,
struct drm_plane *plane;
const struct drm_plane_state *pstate;
struct intel_plane_state *intel_pstate;
- int crtc_clock, cdclk;
+ int crtc_clock, dotclk;
uint32_t pipe_max_pixel_rate;
uint_fixed_16_16_t pipe_downscale;
uint_fixed_16_16_t max_downscale = u32_to_fixed_16_16(1);
@@ -4157,11 +4157,15 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc
*intel_crtc,
pipe_downscale = mul_fixed16(pipe_downscale, max_downscale);
crtc_clock = crtc_state->adjusted_mode.crtc_clock;
- cdclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
- pipe_max_pixel_rate = div_round_up_u32_fixed16(cdclk, pipe_downscale);
+ dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
+
+ if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)))
+ dotclk *= 2;
+
+ pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
if (pipe_max_pixel_rate < crtc_clock) {
- DRM_ERROR("Max supported pixel clock with scaling exceeded\n");
+ DRM_DEBUG_KMS("Max supported pixel clock with scaling
exceeded\n");
return -EINVAL;
}
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