Same as with FDI RX, Lynx point only has one transcoder, which can be
driven by any pipe. So consider that only pipeA will be used with CRT for
now.
Signed-off-by: Eugeni Dodonov <eugeni.dodo...@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 19 +++++++++++++++----
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index e8fd6cc..d7b337b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1660,11 +1660,12 @@ static void intel_enable_transcoder(struct
drm_i915_private *dev_priv,
/* PCH only available on ILK+ */
BUG_ON(dev_priv->info->gen < 5);
+ /* On LPT, there is only one transcoder, but any pipe can be used with
+ * it. To simplify things, we consider that only pipeA can be used
+ * with CRT, so we handle this check in the same way as with the FDI
+ * receiver.
+ */
if (HAS_PCH_LPT(dev_priv->dev)) {
- /* On LPT, there is only one transcoder, but any pipe can be
used with it.
- * To simplify things, we consider that only pipeA can be used
with CRT,
- * so we handle this check in the same way as with the FDI
receiver.
- */
if (pipe > 0) {
DRM_ERROR("Attempting to enable transcoder on Lynx
point with pipe > 0\n");
return;
@@ -1714,6 +1715,16 @@ static void intel_disable_transcoder(struct
drm_i915_private *dev_priv,
int reg;
u32 val;
+ /* On Lynx Point, there is only one transcoder, which we assume it is
+ * mapped into pipe 0 for simplicity.
+ */
+ if (HAS_PCH_LPT(dev_priv->dev)) {
+ if (pipe > 0) {
+ DRM_ERROR("Attempting to disable transcoder on Lynx
Point with pipe > 0\n");
+ return;
+ }
+ }
+
/* FDI relies on the transcoder */
assert_fdi_tx_disabled(dev_priv, pipe);
assert_fdi_rx_disabled(dev_priv, pipe);
--
1.7.11.1
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