Chris Wilson <ch...@chris-wilson.co.uk> writes: > On Thu, 21 Jun 2012 18:13:19 -0700, Keith Packard <kei...@keithp.com> wrote:
> It was structured to minimise lane count because certain chipsets did > not wire up all the lanes, right? Is that still relevant as we are using > the advertised max_lane_count from the DPCD now? We've always used the max_lane_count from dpcd; has there been some recent change that fixed usage of that? What I recall is one acer laptop that advertised 4 lanes but had only wired up two of them. -- keith.pack...@intel.com
pgpmKQkYSOOOJ.pgp
Description: PGP signature
_______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
