Chris Wilson <ch...@chris-wilson.co.uk> writes: > Defer actual enabling of RPS to the set rps routine, called upon > enabling and so we only start RPS when all thresholds have been set. > > Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> > Cc: sta...@vger.kernel.org
As discussed in irc, we will need a followup cleanup as the function names deviate from the actual content. Reviewed-by: Mika Kuoppala <mika.kuopp...@intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 15 ++++++++++----- > 1 file changed, 10 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 169c4908ad5b..a40ad32d76eb 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5344,9 +5344,17 @@ static void gen9_enable_rps(struct drm_i915_private > *dev_priv) > > I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); > > + I915_WRITE(GEN6_RP_CONTROL, > + GEN6_RP_MEDIA_TURBO | > + GEN6_RP_MEDIA_HW_NORMAL_MODE | > + GEN6_RP_MEDIA_IS_GFX | > + GEN6_RP_UP_BUSY_AVG | > + GEN6_RP_DOWN_IDLE_AVG); > + > /* Leaning on the below call to gen6_set_rps to program/setup the > - * Up/Down EI & threshold registers, as well as the RP_CONTROL, > - * RP_INTERRUPT_LIMITS & RPNSWREQ registers */ > + * Up/Down EI & threshold registers, as well as the > + * RP_INTERRUPT_LIMITS & RPNSWREQ registers > + */ > reset_rps(dev_priv, gen6_set_rps); > > intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > @@ -5476,7 +5484,6 @@ static void gen8_enable_rps(struct drm_i915_private > *dev_priv) > GEN6_RP_MEDIA_TURBO | > GEN6_RP_MEDIA_HW_NORMAL_MODE | > GEN6_RP_MEDIA_IS_GFX | > - GEN6_RP_ENABLE | > GEN6_RP_UP_BUSY_AVG | > GEN6_RP_DOWN_IDLE_AVG); > > @@ -6042,7 +6049,6 @@ static void cherryview_enable_rps(struct > drm_i915_private *dev_priv) > I915_WRITE(GEN6_RP_CONTROL, > GEN6_RP_MEDIA_HW_NORMAL_MODE | > GEN6_RP_MEDIA_IS_GFX | > - GEN6_RP_ENABLE | > GEN6_RP_UP_BUSY_AVG | > GEN6_RP_DOWN_IDLE_AVG); > > @@ -6100,7 +6106,6 @@ static void valleyview_enable_rps(struct > drm_i915_private *dev_priv) > GEN6_RP_MEDIA_TURBO | > GEN6_RP_MEDIA_HW_NORMAL_MODE | > GEN6_RP_MEDIA_IS_GFX | > - GEN6_RP_ENABLE | > GEN6_RP_UP_BUSY_AVG | > GEN6_RP_DOWN_IDLE_CONT); > > -- > 2.11.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
