On Fri, Feb 10, 2017 at 12:05:53PM -0800, Michel Thierry wrote: > > On 10/02/17 10:52, Chris Wilson wrote: > >When updating the bookkeeping following the reset, we need the seqno to > >be coherent on the CPU prior to trusting its result for deciding whether > >any request is completed. We need the irq_barrier before we start making > >these decisions, i.e. in reset_prepare. > > > >References: https://bugs.freedesktop.org/show_bug.cgi?id=99733 > >Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> > >Cc: Mika Kuoppala <mika.kuopp...@intel.com> > >--- > > drivers/gpu/drm/i915/i915_gem.c | 6 +++--- > > 1 file changed, 3 insertions(+), 3 deletions(-) > > > > I havent seen the issue in the platforms I have, but makes sense.
Ironlake is the most special of all. There's no flush control available to order the posting of writes and the interrupt, so there's just a big sleep and hope for the best. (Not that the story is any better for gen6/7.) > If you need one, > > Reviewed-by: Michel Thierry <michel.thie...@intel.com> Thanks, -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
