From: Paulo Zanoni <paulo.r.zan...@intel.com>

So the write_infoframe function can assume the DIP is on.

Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
---
 drivers/gpu/drm/i915/intel_hdmi.c |   22 ++++++++++++++--------
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index 30f040b..425e676 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -128,7 +128,6 @@ static void g4x_write_infoframe(struct drm_encoder *encoder,
        val |= g4x_infoframe_index(frame);
 
        val &= ~g4x_infoframe_enable(frame);
-       val |= VIDEO_DIP_ENABLE;
 
        I915_WRITE(VIDEO_DIP_CTL, val);
 
@@ -161,7 +160,6 @@ static void ibx_write_infoframe(struct drm_encoder *encoder,
        val |= g4x_infoframe_index(frame);
 
        val &= ~g4x_infoframe_enable(frame);
-       val |= VIDEO_DIP_ENABLE;
 
        I915_WRITE(reg, val);
 
@@ -195,13 +193,9 @@ static void cpt_write_infoframe(struct drm_encoder 
*encoder,
 
        /* The DIP control register spec says that we need to update the AVI
         * infoframe without clearing its enable bit */
-       if (frame->type == DIP_TYPE_AVI)
-               val |= VIDEO_DIP_ENABLE_AVI;
-       else
+       if (frame->type != DIP_TYPE_AVI)
                val &= ~g4x_infoframe_enable(frame);
 
-       val |= VIDEO_DIP_ENABLE;
-
        I915_WRITE(reg, val);
 
        for (i = 0; i < len; i += 4) {
@@ -233,7 +227,6 @@ static void vlv_write_infoframe(struct drm_encoder *encoder,
        val |= g4x_infoframe_index(frame);
 
        val &= ~g4x_infoframe_enable(frame);
-       val |= VIDEO_DIP_ENABLE;
 
        I915_WRITE(reg, val);
 
@@ -356,6 +349,8 @@ void g4x_set_infoframes(struct drm_encoder *encoder,
                return;
        }
 
+       val |= VIDEO_DIP_ENABLE;
+
        I915_WRITE(reg, val);
 
        intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
@@ -396,6 +391,8 @@ void ibx_set_infoframes(struct drm_encoder *encoder,
                return;
        }
 
+       val |= VIDEO_DIP_ENABLE;
+
        I915_WRITE(reg, val);
 
        intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
@@ -421,6 +418,11 @@ void cpt_set_infoframes(struct drm_encoder *encoder,
                return;
        }
 
+       /* Set both together, unset both together: see the spec. */
+       val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
+
+       I915_WRITE(reg, val);
+
        intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
        intel_hdmi_set_spd_infoframe(encoder);
 }
@@ -444,6 +446,10 @@ void vlv_set_infoframes(struct drm_encoder *encoder,
                return;
        }
 
+       val |= VIDEO_DIP_ENABLE;
+
+       I915_WRITE(reg, val);
+
        intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
        intel_hdmi_set_spd_infoframe(encoder);
 }
-- 
1.7.10

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