The workaround WaSetHdcUnitClockGatingDisableInUcgctl6 applies only
until BXT B0 according to bspec.
Cc: Imre Deak <imre.d...@intel.com>
Signed-off-by: Ander Conselvan de Oliveira
<ander.conselvan.de.olive...@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 148cd1e..b257343 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -89,11 +89,13 @@ static void bxt_init_clock_gating(struct drm_i915_private
*dev_priv)
GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
/*
+ * WaSetHdcUnitClockGatingDisableInUcgctl6:bxt
* FIXME:
* GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
*/
- I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
- GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
+ I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
+ GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
/*
* WaDisablePWMClockGating:bxt
--
2.5.5
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